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公开(公告)号：KR1019960010924B1
公开(公告)日：1996-08-13
申请号：KR1019920026630
申请日：1992-12-30
Applicant: 한국전자통신연구원
IPC: G06F3/12
Abstract: The method is for confronting the change of the position to install a printer effectively and for enabling several users to share the printer easily without installing an expensive printer server. The method comprises: the step of connecting a printer to a serial port of NIU(Network Interface Unit) using a terminal server, and allotting a network address and changing parameters to be appropriate to the printer; and the step that a printer demon or a printer spooler of systems forms a stream from a standard input to a communication channel through a network by using a communication socket.
Abstract translation: 该方法是面对更换打印机的位置，有效地安装打印机，并使多个用户能够轻松共享打印机，而无需安装昂贵的打印机服务器。 该方法包括：使用终端服务器将打印机连接到NIU的串行端口（网络接口单元）的步骤，以及分配网络地址并改变适合于打印机的参数; 以及系统的打印机恶魔或打印机后台处理程序通过使用通信套接字通过网络从标准输入形成流到通信信道的步骤。
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公开(公告)号：KR1019940009755B1
公开(公告)日：1994-10-17
申请号：KR1019910024250
申请日：1991-12-24
Applicant: 한국전자통신연구원
IPC: G06F9/00
Abstract: The memory board contains an initialization control circuit (30) to remove an error due to random check bits during the access of data in the memory after supply of power. The circuit writes an initial value into data storage area and error correction area of a memory (10) as soon as power is supplied. The memory board also contains an error correction and detection module (20), a binary counter (40) to generate the memory address during the initialization, and a register (60) to store "0" value into data area of memory during the initialization.
Abstract translation: 存储器板包含初始化控制电路（30），用于在供电之后在存储器中的数据访问期间消除由于随机校验位导致的错误。 一旦电力供应，电路将初始值写入存储器（10）的数据存储区域和纠错区域。 存储器板还包含纠错和检测模块（20），用于在初始化期间产生存储器地址的二进制计数器（40）以及在初始化期间将“0”值存储到存储器的数据区域中的寄存器（60） 。
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Patent Agency Ranking
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公开(公告)号：KR1019940015843A
公开(公告)日：1994-07-21
申请号：KR1019920025008
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: 본 발명은 동기형 버스를 채용한 다중처리기 시스템에서 프로세서 보드들간의 데이타 전송을 지원하는 방법에 관한 것으로, 하나의 프로세서 보드가 필요로 하는 데이타가 어떤 메모리 보드에 있지만 실제로 유효한 데이타가 다른 하나의 프로세서 보드에 있어면 메모리 보드에 대한 참조없이 두 프로세서 보드간에 직접 데이타의 송수신이 가능하게 한다.
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公开(公告)号：KR1019940005779B1
公开(公告)日：1994-06-23
申请号：KR1019910025589
申请日：1991-12-31
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit for informing shared state and altered state of cache data comprises a program device for generating combination signals, first and second D flip-flops for setting their outputs to 1, and a third D filp-flop for setting its output to 0, thereby maintaining cache data coherence.
Abstract translation: 用于通知高速缓存数据的共享状态和改变状态的电路包括用于产生组合信号的程序设备，用于将其输出设置为1的第一和第二D触发器，以及用于将其输出设置为0的第三D滤波器 维护缓存数据一致性。
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