公开(公告)号：ITMI20042073A1

公开(公告)日：2005-01-29

申请号：ITMI20042073

申请日：2004-10-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

公开(公告)号：DE69630678T2

公开(公告)日：2004-09-23

申请号：DE69630678

申请日：1996-05-13

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/12 ,  G11C7/00

Abstract: A column select multiplexer for a memory array organized in modules, each module handling two sets or bunches each of a certain minimum number of bitlines, is realized in a space opposite to the bitlines terminations and the select transistors are realized along a uninterrupted active area strip by realizing isolation gates between adjacent diffusions of two distinct select transistors. The bitlines of the two bunches handled by a multiplexer module are preferably interleaved and the respective select transistors are realized along two parallel uninterrupted active area strips.

公开(公告)号：DE69631821D1

公开(公告)日：2004-04-15

申请号：DE69631821

申请日：1996-04-09

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/12 ,  G11C7/14 ,  G11C16/24 ,  G11C7/00 ,  G11C16/06

公开(公告)号：DE69630943D1

公开(公告)日：2004-01-15

申请号：DE69630943

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/06

Abstract: The circuit (2) includes a memory element (33) connected to an enabling input (15) receiving an enabling signal (ATD), and in turn including a first reset circuit (45) receiving an internal reset signal (RES), and a second reset circuit (44) receiving an external timing control signal (OE), to generate an operating step enabling signal (PCn) having a first switching edge on receiving the enabling signal (ATD), a second switching edge on receiving the reset signal (RES), and a third switching edge on receiving the external timing control signal (OE). A control input (13) receives a timing mode signal (TLEV), and is connected to the first and second reset circuits (45, 44) to enable them selectively. By enabling the second reset circuit (44) and supplying the external timing control signal (OE), in successive cycles, with different delays in relation to the enabling signal (ATD), different readings of the memory are enabled to characterize the response and optimize the timing of the memory device.

公开(公告)号：DE69630672D1

公开(公告)日：2003-12-18

申请号：DE69630672

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C16/28 ,  G11C16/06

Abstract: A reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories, which comprises: a first branch for connecting a first load (1) and a memory cell matrix; a second branch for connecting a second load (1') and at least one virgin reference memory cell (4'); means (YM, YN) for selecting a memory cell (4) of the memory matrix; and means (YM, YN) for selecting at least one virgin reference cell (4'); each one of the first and second branches having a transistor (2, 2') for enabling the flow of current respectively between the first load (1) and the second load (1') and the memory cell matrix and the at least one reference memory cell (4'); the enabling transistors (2, 2') being controlled, respectively, by a first biasing structure (3) and by a second biasing structure (3'). The reference system has the particularity that it comprises at least one transistor (5) for redistributing the current of the load (1) on the first branch, which is connected in parallel to the enabling transistor (2), and a first equalization transistor (6) that is controlled by a precharge signal (PC) for the equalization of opposite nodes of the first and second branches; the at least one current redistribution transistor (5) provides a current imbalance in the first load (1) and in the second load (1') to sense the difference in conductivity between a memory cell (4) of the memory matrix and the at least one reference cell (4'), in order to determine the programmed or non-programmed status of the memory cell (4) of the memory matrix.

公开(公告)号：DE69626815T2

公开(公告)日：2003-12-11

申请号：DE69626815

申请日：1996-09-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/10 ,  G11C7/00

Abstract: The invention relates to a control circuit (1) for an output buffer, of the type which comprises a first input terminal (I1) receiving a first enable signal (OEn) and a second input terminal (I2) receiving a second enable signal (CEn), as well as first (O1) and second (O2) output terminals to generate first (OE_L) and second (OE_H) partial enable signals to transfer discrete sets of data bits, the first (I1) and second (I2) input terminals being coupled to the first (O1) and second (O2) output terminals through a multiplexer (2), the control circuit (1) comprising a synchronization circuit (7) for linking the partial enable signals (OE_L,OE_H) operatively to a synchronization signal (SYNC) of the pulse type being synchronous with the loading of the output buffer, the synchronization circuit (7) being connected between an output terminal (O3) of said multiplexer (2) and the first (O1) and second (O2) output terminals of the control circuit (1).

公开(公告)号：DE69630108D1

公开(公告)日：2003-10-30

申请号：DE69630108

申请日：1996-04-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/22 ,  G11C7/00

公开(公告)号：DE69531823D1

公开(公告)日：2003-10-30

申请号：DE69531823

申请日：1995-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

公开(公告)号：IT1318979B1

公开(公告)日：2003-09-19

申请号：ITMI20002165

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C7/10 ,  G11C8/12 ,  G11C16/08

Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

公开(公告)号：ITMI20012795A1

公开(公告)日：2003-06-24

申请号：ITMI20012795

申请日：2001-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: H03M5/00

Abstract: A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example.