公开(公告)号：US11895778B2

公开(公告)日：2024-02-06

申请号：US17552907

申请日：2021-12-16

Applicant: AMULAIRE THERMAL TECHNOLOGY, INC.

Inventor： Shih-Hsi Tai ,  Tung-Ho Tao ,  Tze-Yang Yeh

IPC: H05K1/02 ,  H05K3/06

CPC classification number: H05K3/061 ,  H05K1/0207 ,  H05K2201/0166

Abstract: An etching method for manufacturing a substrate structure having a thick electrically conductive layer, and a substrate structure having a thick electrically conductive layer are provided. The etching method includes providing an electrically insulating substrate structure including a thermally conductive and electrically insulating layer, an electrically conductive layer, and a non-photosensitive polymer masking layer, removing one part of the non-photosensitive polymer masking layer and one part of the electrically conductive layer by a machining process to form at least one electrically conductive recess having the electrically conductive layer exposed, forming a predetermined thickness ratio between a thickness of the electrically conductive recess and a thickness of the electrically conductive layer, removing a reserved part of the electrically conductive layer between a bottom wall of the electrically conductive recess and a bottom surface of the electrically conductive layer, and removing a remaining part of the non-photosensitive polymer masking layer.

公开(公告)号：US20230189444A1

公开(公告)日：2023-06-15

申请号：US17955683

申请日：2022-09-29

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Gao HUANG ,  Benxia HUANG ,  Yejie HONG

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K1/186 ,  H05K1/113 ,  H05K1/0366 ,  H05K3/0035 ,  H05K3/4661 ,  H05K3/429 ,  H05K2201/032 ,  H05K2201/09509 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2203/061 ,  H05K2203/308

Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

公开(公告)号：US20180150672A1

公开(公告)日：2018-05-31

申请号：US15421880

申请日：2017-02-01

Applicant: Primax Electronics Ltd.

Inventor： MAO-HSIU HSU ,  KUAN-PAO TING

IPC: G06K9/00 ,  H05K1/18 ,  H05K1/02 ,  H04L29/06 ,  H04W12/06

CPC classification number: G06K9/00013 ,  G06K9/00087 ,  H04L63/0861 ,  H04W12/06 ,  H05K1/0212 ,  H05K1/181 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2201/10151 ,  Y02P70/611

Abstract: A fingerprint identification module is provided for identifying a fingerprint of a finger. The fingerprint identification module includes a sensing chip and a thermally deformable layer. The thermally deformable layer is disposed over the sensing chip and includes a sensing region. When the finger is placed on the sensing region, the fingerprint of the finger is sensed by the sensing chip. If the fingerprint identification result of the fingerprint identification module fails, the thermally deformable layer is firstly changed to a molten state and then returned to a solidified state within a predetermined time period. Consequently, the finger is fixed by the thermally deformable layer.

公开(公告)号：US20160233109A1

公开(公告)日：2016-08-11

申请号：US15099690

申请日：2016-04-15

Applicant: Tessera, Inc.

Inventor： Kazuo Sakuma ,  Philip Damberg ,  Belgacem Haba

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H05K3/00

CPC classification number: H01L21/4853 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/01 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0284 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/002 ,  H05K2201/0166 ,  H01L2924/00

Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

公开(公告)号：US08756804B2

公开(公告)日：2014-06-24

申请号：US13213984

申请日：2011-08-19

Applicant: Hyung Jin Jeon ,  Young Do Kweon ,  Seung Wook Park ,  Seon Hee Moon

Inventor： Hyung Jin Jeon ,  Young Do Kweon ,  Seung Wook Park ,  Seon Hee Moon

IPC: H01K3/10

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/036 ,  H05K3/42 ,  H05K3/4602 ,  H05K3/4605 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/0594 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.

Abstract translation: 公开了一种印刷电路板，包括基底构件，形成在基底构件的两个表面中的每一个上的绝缘层，使得基底构件的表面变平，形成在绝缘层上的电路层和用于连接的通孔 所述电路层形成在所述基底构件的一个表面上，所述电路层形成在所述基底构件的另一个表面上。 还提供了制造印刷电路板的方法。

公开(公告)号：US20110232942A1

公开(公告)日：2011-09-29

申请号：US13069741

申请日：2011-03-23

Applicant: Hiroyuki UEMATSU

Inventor： Hiroyuki UEMATSU

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K3/427 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0166 ,  H05K2201/0355 ,  H05K2201/10977 ,  Y10T29/49124

Abstract: A multi-layer wiring board includes a substrate; a land including a first conductive member arranged on the substrate; a second conductive member that is deposited on a surface of the first conductive member, which is a surface distant from the substrate; and a stress relaxation layer arranged between the first conductive member and the second conductive member; and a connection portion that makes contact with the land and that is electrically connected to the land.

Abstract translation: 多层布线基板包括基板; 包括布置在所述基板上的第一导电构件的平台; 第二导电构件，其沉积在所述第一导电构件的表面上，所述第一导电构件是远离所述衬底的表面; 以及布置在所述第一导电构件和所述第二导电构件之间的应力松弛层; 以及与该焊盘接触并且与该焊盘电连接的连接部。

公开(公告)号：US07944029B2

公开(公告)日：2011-05-17

申请号：US12560727

申请日：2009-09-16

Applicant: Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

Inventor： Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

IPC: H01L23/48

CPC classification number: H05K3/28 ,  G11C16/0483 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/83191 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/24 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3452 ,  H05K2201/0166 ,  H05K2201/0769 ,  H05K2201/10159 ,  H05K2201/10575 ,  H05K2203/049 ,  H05K2203/1316 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided.

Abstract translation: 移动离子扩散导致存储芯片中的非易失性存储元件的阈值电压的偏移，例如在存储器芯片的组装过程中。 为了减少或避免这种偏移，可以将涂层施加到印刷电路板基板或表面安装存储芯片的引导框架。 可以使用厚度约为10μm的丙烯酸树脂涂层。 使用粘合膜将记忆芯片附着到涂层上。 也可以使用堆叠的芯片。 另一种方法在焊接掩模层内提供印刷电路板的铜迹线上的金属阻挡迹线。 金属阻挡迹线以与铜迹线相同的图案制造，但是更宽，使得它们至少部分地包围和包围铜迹线。 提供相应的装置和制造工艺。

公开(公告)号：US20110108519A1

公开(公告)日：2011-05-12

申请号：US13006135

申请日：2011-01-13

Applicant: Katsuya SAKAYORI ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

Inventor： Katsuya SAKAYORI ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

IPC: H05K3/00

CPC classification number: H01L21/31138 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32134 ,  H05K1/0346 ,  H05K1/056 ,  H05K3/002 ,  H05K3/064 ,  H05K2201/0154 ,  H05K2201/0166

Abstract: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable by a wet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layer-insulating layer-second inorganic material layer or a layer construction of inorganic material layer-insulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.

Abstract translation: 本发明涉及一种层叠体中的绝缘体，其可以在使用时抑制除尘，更具体地说，涉及绝缘体的电子电路部件，特别是无线悬架。 绝缘体包括可通过湿法蚀刻的一个或多个绝缘单元层的层压体，该绝缘体在湿蚀刻之后已进行等离子体处理。 绝缘体主要作为具有第一无机材料层 - 绝缘层 - 第二无机材料层的层结构或无机材料层 - 绝缘层的层结构的层叠体的绝缘体存在，并且至少一部分无机材料层 已经被去除以暴露绝缘层。

公开(公告)号：US20100203713A1

公开(公告)日：2010-08-12

申请号：US12733595

申请日：2008-09-05

Applicant: Tadahiro Ohmi ,  Makoto Fujimura ,  Tadashi Koike ,  Akinori Bamba ,  Akihiro Kobayashi ,  Kohei Watanuki

Inventor： Tadahiro Ohmi ,  Makoto Fujimura ,  Tadashi Koike ,  Akinori Bamba ,  Akihiro Kobayashi ,  Kohei Watanuki

IPC: H01L21/28 ,  H01L21/20

CPC classification number: H05K3/048 ,  H01L21/0331 ,  H01L27/1288 ,  H01L29/66765 ,  H05K1/0306 ,  H05K3/107 ,  H05K2201/0166 ,  H05K2201/0175

Abstract: An object of this invention is to provide a method for manufacturing an electronic device wherein a conductor layer is uniformly formed on a substrate having a super large area. In the method for manufacturing the electronic device, a metal film for forming a gate electrode is selectively embedded in a transparent resin film formed on a substrate, and the metal film is formed by sputtering directly on the substrate at the gate electrode portion, and on an insulating coat film on portions other than the gate electrode portion. The metal film on the insulating coat film is removed by chemical liftoff with removal of the insulating coat film by etching.

Abstract translation: 本发明的目的是提供一种电子器件的制造方法，其中导体层均匀地形成在具有超大面积的基片上。 在电子设备的制造方法中，用于形成栅电极的金属膜选择性地嵌入到形成在基板上的透明树脂膜中，并且金属膜通过在栅电极部分处直接溅射在基板上而形成， 在除了栅电极部分之外的部分上的绝缘涂膜。 通过化学剥离除去绝缘涂膜上的金属膜，通过蚀刻除去绝缘涂膜。

公开(公告)号：US20080283491A1

公开(公告)日：2008-11-20

申请号：US11987980

申请日：2007-12-06

Applicant: Kunio Arai ,  Hiroshi Aoyama ,  Yasuhiko Kanaya

Inventor： Kunio Arai ,  Hiroshi Aoyama ,  Yasuhiko Kanaya

IPC: H01B13/00

CPC classification number: H05K3/465 ,  B23K26/0604 ,  B23K26/0661 ,  B23K26/0738 ,  B23K26/082 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/35 ,  B23K2101/42 ,  B23K2103/16 ,  B23K2103/42 ,  B23K2103/50 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/045 ,  H05K3/107 ,  H05K3/16 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/09563 ,  H05K2203/0557 ,  H05K2203/108 ,  Y10T29/49155

Abstract: There is provided a printed circuit board whose peel strength is large and a printed circuit board fabrication method and a printed circuit board machining apparatus that allow a fabrication time and a fabrication cost to be reduced. The fabrication method of the printed circuit board comprises steps of forming a resist layer on a surface of the printed circuit board whose surface is made of an insulator, of forming a hole that is connected from the surface of the resist layer to a conductor pattern of an inner layer and a hole and grooves having a depth not connected with the conductor layer of the inner layer by irradiating lasers, of filling a conductive material into the holes and the grooves to form a conductor pattern and of removing the resist layer to project a portion of the conductor pattern out of the surface of the insulating layer.

Abstract translation: 提供了剥离强度大的印刷电路板和允许制造时间和制造成本降低的印刷电路板制造方法和印刷电路板加工装置。 印刷电路板的制造方法包括以下步骤：在其表面由绝缘体制成的印刷电路板的表面上形成抗蚀剂层，形成从抗蚀剂层的表面连接到孔的导体图案 内层和孔以及通过照射激光而不与内层的导体层连接的深度的凹槽，将导电材料填充到孔和凹槽中以形成导体图案并且去除抗蚀剂层以投射 导体图案的部分从绝缘层的表面出来。