公开(公告)号：EP1699277A1

公开(公告)日：2006-09-06

申请号：EP04792430.3

申请日：2004-10-15

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： SAKAI, Norio, Murata Manufacturing Co., Ltd. ,  HARADA, Jun, Murata Manufacturing Co., Ltd. ,  ISHINO, Satoshi, Murata Manufacturing Co., Ltd. ,  NISHIZAWA, Y., Murata Manufacturing Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K1/186 ,  H01L23/5385 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09436 ,  H05K2203/1581 ,  H01L2224/0401

Abstract: A ceramic multilayer substrate is provided with a ceramic laminate (10) including a plurality of ceramic layers laminated, having a first main surface (18), and including internal circuit elements disposed in the inside; a resin layer (15) having a bonding surface (19) in contact with the first main surface (18) of the above-described ceramic laminate (10) and a mounting surface (16) opposite to the above-described bonding surface (19); external electrodes (17), each disposed on the mounting surface (16) of the above-described resin layer (15) and electrically connected to at least one of the internal circuit elements (14) of the above-described ceramic laminate (10); and a ground electrode (12), a dummy electrode, or capacitor-forming electrodes disposed at an interface between the first main surface (18) of the above-described ceramic laminate (10) and the bonding surface (19) of the above-described resin layer (15) or in the inside of the above-described resin layer (15).

Abstract translation: 陶瓷多层基板设置有层叠有多个陶瓷层的陶瓷层压体（10），具有第一主表面（18），并且包括设置在内部的内部电路元件; 具有与上述陶瓷层叠体（10）的第一主面（18）接触的接合面（19）和与上述接合面（19）相对的安装面（16）的树脂层（15） ）; 每个设置在上述树脂层（15）的安装表面（16）上并与上述陶瓷层压板（10）的至少一个内部电路元件（14）电连接的外部电极（17） ; 以及设置在上述陶瓷层叠体（10）的第一主面（18）与上述陶瓷层叠体（10）的接合面（19）之间的界面处的接地电极（12），虚拟电极或电容器形成电极， （15）或上述树脂层（15）的内部。

公开(公告)号：EP1534050A1

公开(公告)日：2005-05-25

申请号：EP04027389.8

申请日：2004-11-18

Applicant: Ruwel AG

Inventor： Ebeling, Ralf ,  van der Kruijs, Ad

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/28 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09436 ,  H05K2201/09454 ,  H05K2201/098

Abstract: Dargestellt und beschrieben ist eine Leiterplatte (1) mit einem Basismaterial (2) aus Isolierstoff als Träger von Leiterbahnen (3), wobei die fertigen Leiterbahnen (3) eine Dicke von mindestens 100 µm aufweisen, sowie ein Verfahren zur Herstellung einer derartigen Leiterplatte (1).
Mit dem erfindungsgemäßen Verfahren kann eine Leiterplatte (1) durch folgende Schritte sehr einfach und zuverlässig hergestellt werden:

Strukturieren der Leiterfolienschicht zur Erzeugung der Leiterbahnen (3),
Verpressen mit einem isolierenden Füllmaterials (8), so daß sowohl die Kanäle (4) zwischen den Leiterbahnen (3) mit dem Füllmaterial (8) vollständig gefüllt als auch die Oberfläche (9) der Leiterbahnen (3) von dem Füllmaterial (8) bedeckt sind und
Anbinden der im Inneren der Leiterplatte (1) angeordneten Leiterbahnen (3) an Anschlußflächen (11) auf der Oberfläche der Leiterplatte (1) durch Bohren und Metallisieren von Löchern (10).

Abstract translation: 电路板包括施加在基材（2）上或导体条（3）上的绝缘填充材料（8），使得条之间的通道被填充材料完全填充，并且带的表面（9）被 填充材料。 孔（10）设置在电路板中，其壁金属化，使得布置在电路板内的导体条通过连接表面（11）电连接到电路板的表面。

公开(公告)号：EP0818946A2

公开(公告)日：1998-01-14

申请号：EP97305014.9

申请日：1997-07-08

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Matsuno, Yukio

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K1/113 ,  H05K1/095 ,  H05K3/0094 ,  H05K3/181 ,  H05K3/247 ,  H05K3/4007 ,  H05K3/429 ,  H05K3/4685 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0959 ,  H05K2203/072

Abstract: A printed-wiring board has a copper foil (the first conductive layer) providing electric conductivity formed on one or both sides of an insulating board providing electrical insulation, an insulating layer providing electrical insulation formed at specific sites (where there are through-holes) on the first conductive layer, and a second conductive layer providing electric conductivity formed on the insulating layer. In this printed-wiring board, when the second conductive layer is formed, deposition of an electrically conductive material by plating, and polishing of the deposited electrically conductive material, these steps are repeated at least once, so that the surface of the second conductive layer can be smoothened to enhance the bonding stability of chip parts.

公开(公告)号：EP0622980B1

公开(公告)日：1997-07-09

申请号：EP94106414.9

申请日：1994-04-25

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tanabe, Kouji ,  Nishioka, Naohiro

IPC: H05K3/32

CPC classification number: H05K3/321 ,  H05K1/0393 ,  H05K1/095 ,  H05K1/114 ,  H05K1/181 ,  H05K3/245 ,  H05K3/4069 ,  H05K3/4644 ,  H05K3/4664 ,  H05K2201/09436 ,  H05K2201/10106 ,  H05K2201/10651 ,  H05K2201/10977 ,  H05K2203/0285 ,  H05K2203/065 ,  H05K2203/1311 ,  H05K2203/1453 ,  Y10T29/4913 ,  Y10T29/49144

公开(公告)号：EP0622980A1

公开(公告)日：1994-11-02

申请号：EP94106414.9

申请日：1994-04-25

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tanabe, Kouji ,  Nishioka, Naohiro

IPC: H05K3/32

CPC classification number: H05K3/321 ,  H05K1/0393 ,  H05K1/095 ,  H05K1/114 ,  H05K1/181 ,  H05K3/245 ,  H05K3/4069 ,  H05K3/4644 ,  H05K3/4664 ,  H05K2201/09436 ,  H05K2201/10106 ,  H05K2201/10651 ,  H05K2201/10977 ,  H05K2203/0285 ,  H05K2203/065 ,  H05K2203/1311 ,  H05K2203/1453 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: The invention concerns a method for mounting electronic components and a related flexible printed circuit board. This board is constituted with a first insulation film (1) covering a first insulating resist layer (3), a second insulation film (7) covering a second insulating resist layer (6) and a printed circuit (4) formed between the first insulating resist layer (3) and the second insulating resist layer (6), and a terminal (5a) of an electronic component (5) is disposed on the printed circuit (4), and the second insulation film (7) is pressed and heated.

Abstract translation: 本发明涉及用于安装电子元件和相关的柔性印刷电路板的方法。 此板与（1），其覆盖第一绝缘的第一绝缘膜构成的抗蚀剂层（7）覆盖的第二绝缘（3），第二绝缘膜的抗蚀剂层（6）和印刷电路（4）在第一绝缘间形成 抗蚀剂层（3）和第二绝缘抗蚀剂层（6），以及电子部件（5）设置在所述印刷电路（4）上，并且第二绝缘膜 - 被按下（7）中，加热的端子（5a）中 ，

公开(公告)号：EP3292885A1

公开(公告)日：2018-03-14

申请号：EP17183909.5

申请日：2017-07-31

Applicant: BIOTRONIK SE & Co. KG

Inventor： Bihler, Eckardt ,  Hauer, Marc ,  Schulze, Daniel

IPC: A61N1/05 ,  A61B5/042 ,  H05K1/02

CPC classification number: H01B5/14 ,  A61B5/042 ,  A61B5/6853 ,  A61B5/686 ,  A61B5/6876 ,  A61B2562/0209 ,  A61B2562/164 ,  A61N1/05 ,  H05K1/0283 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/056 ,  H05K2201/09263 ,  H05K2201/09436

Abstract: Dehnbare Elektrodenleiteranordnung für ein medizinisches Implantat, die mindestens einen zickzack- oder mäanderförmigen Leiterzug auf einem isolierenden Träger und mit einer isolierenden, mit dem Träger unter Einbettung des Leiterzuges dicht verbundenen Abdeckung aufweist, wobei der Träger ein im Wesentlichen nicht dehnbares Material aufweist und in Anpassung an die Kontur des Leiterzuges oder der Leiterzüge zickzack- oder mäanderförmig zugeschnitten ist.

Abstract translation: 对于具有至少一个锯齿形或在绝缘支撑，并与绝缘蜿蜒导体的轨道，与通过嵌入导体运行紧紧地连接盖，所述支撑件包括一个基本上不可拉伸的材料支撑的医用植入物和在适应拉伸电极导体配置 导体轨迹或导体轨迹的轮廓以锯齿形或曲折形切割。

公开(公告)号：EP2018666B1

公开(公告)日：2011-04-06

申请号：EP07718446.3

申请日：2007-05-15

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： VORABERGER, Hannes ,  SCHMID, Gerhard ,  RIESTER, Markus ,  STAHR, Johannes

IPC: H01L23/498 ,  H05K1/18

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/186 ,  H05K3/005 ,  H05K3/107 ,  H05K3/4644 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/09436 ,  H05K2201/10734 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a method for fixing an electronic component (3) on a printed circuit board (2), and contact-connecting the electronic component (3) to the printed circuit board (2), the following steps are provided: - providing the printed circuit board (2) having a plurality of contact and connection pads (8), - providing the electronic component (3) having a number of contact and connection locations (5) corresponding to the plurality of contact and connection pads (8) of the printed circuit board (2), with a mutual spacing reduced in comparison with the spacing of the contact and connection pads (8) of the printed circuit board (2), and – arranging or forming at least one interlayer (4) for routing the contact and connection locations (5) of the electronic component (3) between the contact and connection pads (8) of the printed circuit board (2) and the contact and connection locations (5) of the electronic component (3). A method for producing an interlayer (4) for routing and a system having a printed circuit board (2) and an electronic component (3) using the interlayer (4) for routing are also provided.

公开(公告)号：EP1843391A4

公开(公告)日：2009-12-30

申请号：EP06811611

申请日：2006-10-11

Applicant: MURATA MANUFACTURING CO

Inventor： KIMURA MASAHIRO ,  SAITO YOSHIFUMI

IPC: H01L23/12 ,  H01L25/00 ,  H01L25/04 ,  H01L25/18 ,  H05K1/14 ,  H05K3/46

CPC classification number: H05K1/141 ,  H01L23/15 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/48 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/183 ,  H05K3/284 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/10477 ,  H05K2203/308 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：EP2023697A1

公开(公告)日：2009-02-11

申请号：EP07744278.8

申请日：2007-05-28

Applicant: Fujikura, Ltd.

Inventor： HIRATA, Shuzo ,  ONO, Akinobu

IPC: H05K1/11

CPC classification number: H05K1/117 ,  H05K1/095 ,  H05K3/247 ,  H05K3/28 ,  H05K2201/035 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09709

Abstract: A wiring substrate is provided with a substrate, a conductive circuit formed on a surface of the substrate, and an insulating layer which covers the conductive circuit. In a fitting portion of the wiring substrate, the insulating layer is formed with an opening portion through which a portion of the conductive circuit is exposed or displayed as an exposed surface. On the exposed surface of the conductive circuit, an electrode layer is formed which is made of a conductive member. A bottom surface of the electrode layer is connected to the conductive circuit. An upper surface of the electrode layer is extended in the widthwise direction W of wirings of the conductive circuit so as to cover even a part of the insulating layer.

Abstract translation: 布线基板设置有基板，形成在基板的表面上的导电电路以及覆盖导电电路的绝缘层。 在配线基板的配合部分中，绝缘层形成有开口部分，导电电路的一部分通过开口部分暴露或显示为暴露表面。 在导电电路的暴露表面上，形成由导电构件制成的电极层。 电极层的底表面连接到导电电路。 电极层的上表面在导电电路的配线的宽度方向W上延伸，以便覆盖绝缘层的一部分。

公开(公告)号：EP1805799A1

公开(公告)日：2007-07-11

申请号：EP05794401.9

申请日：2005-10-18

Applicant: Koninklijke Philips Electronics N.V.

Inventor： VAN VEEN, Nicolaas

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01041 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K2201/09436 ,  H05K2201/09745 ,  Y02P70/613

Abstract: A substrate (10) with first metallic contact pads (13a..13d) is disclosed, which first contact pads (13a..13d) and second contact pads (23a..23d) on a second substrate (20) are to be soldered together. According to the invention, the greatest planar extension (Din) of said first contact pads (13a..13d) with respect to said first surface does not exceed 20 µm. Thus, a stand off Xin of zero or almost zero can be achieved when the first substrate (10) and the second substrate (20) are soldered together. This method for instance is applicable to the flip chip technology, wherein preferably "underbump metallization", UBM for short, and "Immersion solder bumping", ISB for short, are used for manufacturing said substrate (10).

Abstract translation: 公开了一种具有第一金属接触焊盘（13a..13d）的衬底（10），第二衬底（20）上的第一接触焊盘（13a..13d）和第二接触焊盘（23a ... 23d）将被焊接 一起。 根据本发明，所述第一接触焊盘（13a..13d）相对于所述第一表面的最大平面延伸（Din）不超过20μm。 因此，当将第一基板（10）和第二基板（20）焊接在一起时，可以实现零或几乎为零的支架。 例如，该方法适用于倒装芯片技术，其中优选使用“底部焊接金属化”，简称为UBM，简称为“浸焊焊料凸块”，用于制造所述衬底（10）。