公开(公告)号：US20090296310A1

公开(公告)日：2009-12-03

申请号：US12132316

申请日：2008-06-03

Applicant: Azuma Chikara

Inventor： Azuma Chikara

IPC: H05K1/18 ,  H01G4/30 ,  H01L21/50

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A capacitive precursor (100) and packaged semiconductor devices therefrom includes a substrate (105), a plurality of electrically conductive material layers (111-118) stacked on the substrate (105). The plurality of electrically conductive layers (111-118) provide first and second patterns (200 and 250). The first patterns (200) each include at least a first pair of overlaying areas free of the electrically conductive material, and the second patterns (250) each include at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. A plurality of dielectric layers (101-107) are interposed between neighboring electrically conductive material layers (111-118) for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Abstract translation: 电容前驱体（100）及其封装的半导体器件包括衬底（105），堆叠​​在衬底（105）上的多个导电材料层（111-118）。 多个导电层（111-118）提供第一和第二图案（200和250）。 第一图案（200）各自包括至少第一对无导电材料的重叠区域，并且第二图案（250）各自包括至少第二对不含导电材料的重叠区域。 第一对区域覆盖具有导电材料的第二图案的区域，并且第二对区域覆盖具有导电材料的第一图案的区域。 在相邻的导电材料层（111-118）之间插入多个电介质层（101-107），用于电隔离。 一个或多个电容性前体可以掉落到基板上或者在组装封装的半导体器件期间并且具有与连接在一起的相应板相关联的导电层，以在组装期间使用传统的组装步骤形成电容器。

公开(公告)号：US07499258B2

公开(公告)日：2009-03-03

申请号：US11319722

申请日：2005-12-29

Applicant: Chang Hoon Shim ,  Jin Yong An ,  Suk Hyeon Cho ,  Sung Hyung Kang

Inventor： Chang Hoon Shim ,  Jin Yong An ,  Suk Hyeon Cho ,  Sung Hyung Kang

IPC: H01G4/236 ,  H01G4/06

CPC classification number: H01G2/06 ,  H01G4/232 ,  H01G4/30 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10643 ,  H01L2924/00

Abstract: The invention provides an embedded multilayer chip capacitor, and a printed circuit board having the same. The embedded multilayer chip capacitor has a capacitor body having a plurality of dielectric layers stacked one on another; a plurality of first and second internal electrodes formed inside the capacitor body, separated by the dielectric layers; and first and second vias extended vertically inside the capacitor body. The first via is connected to the first internal electrodes and the second via is connected to the second internal electrodes. The first via is led to a bottom of the capacitor body and the second via is led to a top of the capacitor body.

Abstract translation: 本发明提供一种嵌入式多层片状电容器及具有该电容器的印刷电路板。 嵌入式多层片状电容器具有电容器主体，该电容器本体具有彼此层叠的多个电介质层; 多个第一和第二内部电极，形成在电容器本体内部，被电介质层分隔开; 并且第一和第二通孔在电容器体内垂直延伸。 第一通孔连接到第一内部电极，第二通孔连接到第二内部电极。 第一通孔被引导到电容器主体的底部，第二通孔被引导到电容器主体的顶部。

公开(公告)号：US07417870B2

公开(公告)日：2008-08-26

申请号：US11709156

申请日：2007-02-22

Applicant: Sung Taek Lim ,  Yul Kyo Chung

Inventor： Sung Taek Lim ,  Yul Kyo Chung

IPC: H05K1/18

CPC classification number: H05K1/0231 ,  H01L2924/15311 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A multi-layer board having a superior decoupling function in a low frequency band and a radio frequency band. The multi-layer board includes a board body having a plurality of stacked dielectric layers, power terminals connected through a via, ground terminals connected through a via and an integrated circuit component connected to the power and ground terminals. The multi-layer board also includes a power line unit connected to the power terminals and the integrated circuit component and a ground line unit connected to the ground terminals and the integrated circuit component. The multi-layer board further includes at least one multilayer chip capacitor mounted on the board body and connected between the power terminal and the ground terminal formed on the board body and at least one thin film capacitor mounted inside the board body and connected between the power line unit and the ground line unit.

Abstract translation: 一种在低频带和无线电频带中具有优异的去耦功能的多层板。 多层板包括具有多层堆叠电介质层的电路板，通过通孔连接的电源端子，通过通孔连接的接地端子和连接到电源接地端子的集成电路部件。 多层板还包括连接到电源端子和集成电路部件的电力线单元和连接到接地端子和集成电路部件的接地线单元。 多层板还包括安装在板体上并连接在电源端子和形成在电路板主体上的接地端子之间的至少一个多层片式电容器，以及安装在电路板主体内并连接在电源之间的至少一个薄膜电容器 线路单元和地线单元。

公开(公告)号：US20070194876A1

公开(公告)日：2007-08-23

申请号：US11709156

申请日：2007-02-22

Applicant: Sung Taek Lim ,  Yul Kyo Chung

Inventor： Sung Taek Lim ,  Yul Kyo Chung

IPC: H01F27/28

CPC classification number: H05K1/0231 ,  H01L2924/15311 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A multi-layer board having a superior decoupling function in a low frequency band and a radio frequency band. The multi-layer board includes a board body having a plurality of stacked dielectric layers, power terminals connected through a via, ground terminals connected through a via and an integrated circuit component connected to the power and ground terminals. The multi-layer board also includes a power line unit connected to the power terminals and the integrated circuit component and a ground line unit connected to the ground terminals and the integrated circuit component. The multi-layer board further includes at least one multilayer chip capacitor mounted on the board body and connected between the power terminal and the ground terminal formed on the board body and at least one thin film capacitor mounted inside the board body and connected between the power line unit and the ground line unit.

Abstract translation: 一种在低频带和无线电频带中具有优异的去耦功能的多层板。 多层板包括具有多层堆叠电介质层的电路板，通过通孔连接的电源端子，通过通孔连接的接地端子和连接到电源接地端子的集成电路部件。 多层板还包括连接到电源端子和集成电路部件的电力线单元和连接到接地端子和集成电路部件的接地线单元。 多层板还包括安装在板体上并连接在电源端子和形成在电路板主体上的接地端子之间的至少一个多层片式电容器，以及安装在电路板主体内并连接在电源之间的至少一个薄膜电容器 线路单元和地线单元。

公开(公告)号：US20040212063A1

公开(公告)日：2004-10-28

申请号：US10425383

申请日：2003-04-28

Inventor： Edward W. Jaeck ,  Chia-Pin Chiu

IPC: H01L023/48 ,  H01L021/44

CPC classification number: H05K1/147 ,  H01L23/5385 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/023 ,  H05K1/145 ,  H05K1/189 ,  H05K3/361 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic package is provided, having a flexible substrate, a first plurality of conductors, and a second plurality of conductors. The flexible substrate has first and second portions with a fold portion between the first and second portions, and is folded at the fold portion to position the second portion over the first portion. Each one of the first plurality of conductors runs from the first portion over the fold portion onto the second portion. Each one of the second plurality of conductors runs from the first portion onto the second portion without running over the fold portion.

Abstract translation: 提供一种电子封装，具有柔性基板，第一多个导体和第二多个导体。 柔性基板具有在第一和第二部分之间具有折叠部分的第一和第二部分，并且在折叠部分处折叠以将第二部分定位在第一部分上。 第一多个导体中的每一个从折叠部分上的第一部分延伸到第二部分上。 所述第二多个导体中的每一个从所述第一部分延伸到所述第二部分上，而不超过所述折叠部分。

公开(公告)号：US06651315B1

公开(公告)日：2003-11-25

申请号：US09181028

申请日：1998-10-27

Applicant: Gregory A. Graves ,  Michael Mengruo Zhang ,  Daniel Chandler ,  Chi-Ming Chan ,  Shou-Mean Fang ,  Dennis Siden ,  Mark Thompson

Inventor： Gregory A. Graves ,  Michael Mengruo Zhang ,  Daniel Chandler ,  Chi-Ming Chan ,  Shou-Mean Fang ,  Dennis Siden ,  Mark Thompson

IPC: H01C1728

CPC classification number: H05K1/184 ,  H01C1/14 ,  H01C1/1406 ,  H01C7/027 ,  H01C17/06586 ,  H05K1/182 ,  H05K3/0097 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10469 ,  H05K2201/10643 ,  H05K2201/10666 ,  Y02P70/613 ,  Y10T29/49085 ,  Y10T29/49101 ,  Y10T29/49103

Abstract: An electrical device which comprises first and second laminar electrodes and a laminar PTC resistive element sandwiched between them, the device comprising: (a) a main portion which comprises a main part of the first electrode, a main part of the second electrode, and a main part of the resistive element; and (b) a first connection leg which extends away from the main portion and which comprises a first leg part of the first electrode which is integral with the main part of the first electrode, and a first leg part of the resistive element which is integral with the main part of the resistive element. Such devices can be secured to circuit boards in a variety of ways, and to elastically deformed terminals. Preferably preferred devices contain two laminar electrodes, with a PTC element between them, and a cross-conductor which passes through the thickness of the device and contacts one only of the two electrodes. The cross-conductor permits connection to both electrodes from the same side of the device, and also makes it possible to carry out the steps for preparing such devices on an assembly which corresponds to a number of individual devices, with division of the assembly as the final step.

Abstract translation: 一种电气装置，包括第一和第二层状电极和夹在它们之间的层状PTC电阻元件，该装置包括：（a）主要部分，其包括第一电极的主要部分，第二电极的主要部分，以及 电阻元件的主要部分; 和（b）第一连接腿，其远离主要部分延伸并且包括与第一电极的主要部分成一体的第一电极的第一腿部和电阻元件的第一腿部， 电阻元件的主要部分。这些装置可以以各种方式固定到电路板，并且可弹性变形的端子。 优选地，优选的装置包含两个层状电极，其间具有PTC元件，并且穿过该器件的厚度并且仅与两个电极中的一个接触的交叉导体。 交叉导体允许从设备的同一侧连接到两个电极，并且还使得可以在对应于多个单独设备的组件上执行用于准备这样的设备的步骤，将组件划分为 最后一步。

公开(公告)号：US06548207B1

公开(公告)日：2003-04-15

申请号：US09521090

申请日：2000-03-07

Applicant: Mark E. Tuttle

Inventor： Mark E. Tuttle

IPC: H01M642

CPC classification number: H01M2/1066 ,  H01M2/1044 ,  H01M2/204 ,  H01M6/42 ,  H02J7/0024 ,  H04B1/3883 ,  H05K3/321 ,  H05K2201/10037 ,  H05K2201/10515 ,  H05K2201/10643 ,  Y10T29/49108 ,  Y10T29/49114

Abstract: Thin-profile battery circuits and constructions, and in particular button-type battery circuits and constructions and methods of forming the same are described. In one implementation, a substrate is provided having an outer surface with a pair of spaced electrical contact pads thereon. At least two thin-profile batteries are conductively bonded together in a stack having a lowermost battery and an uppermost battery. The batteries include respective positive and negative terminals. The lowermost battery has one of its positive or negative terminals adhesively bonded to one of the pair of electrical contact pads while the uppermost battery has one of its positive or negative terminals electrically connected to the other of the pair of electrical contact pads. The batteries can be provided into parallel or series electrical connections.

Abstract translation: 描述了薄型电池电路和结构，特别是按钮式电池电路及其构成及其形成方法。 在一个实施方案中，提供了具有外表面的衬底，其上具有一对间隔的电接触焊盘。 至少两个薄型电池在具有最低电池和最上面的电池的堆叠中导电地结合在一起。 电池包括相应的正极和负极。 最下面的电池具有一个正极或负极端子，其粘合地粘合到一对电接触焊盘中的一个，而最上面的电池具有与该对电接触焊盘中的另一个电连接的正或负端子中的一个。 电池可以并联或串联电连接。

公开(公告)号：US06504444B1

公开(公告)日：2003-01-07

申请号：US09187868

申请日：1998-11-06

Applicant: Mitsuru Furuya ,  Osamu Myohga ,  Yoshitsugu Okada

Inventor： Mitsuru Furuya ,  Osamu Myohga ,  Yoshitsugu Okada

IPC: H01P136

CPC classification number: H05K1/184 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/086 ,  H05K2201/10416 ,  H05K2201/10643 ,  H01L2924/00

Abstract: Holes are formed in a ceramic substrate before sintering, magnetic parts and dielectric parts are fitted in the holes and the substrate is sintered at a temperature equal to or lower than the sintering temperature of the magnetic parts. It is possible to obtain a very compact high frequency integrated circuit, particularly, a micro wave integrated circuit which can be utilized in a frequency band of several tens GHz, by using hard ferrite as a material of the magnetic parts and magnetizing them after the sintering.

Abstract translation: 在烧结之前，在陶瓷基板中形成孔，将磁性部件和电介质部件嵌合在孔中，并且在等于或低于磁性部件的烧结温度的温度下烧结基板。 可以通过使用硬质铁氧体作为磁性部件的材料并且在烧结之后对它们进行磁化来获得非常紧凑的高频集成电路，特别是可以在几十GHz的频带中使用的微波集成电路 。

公开(公告)号：US06326558B1

公开(公告)日：2001-12-04

申请号：US09354748

申请日：1999-07-29

Applicant: Osamu Maeda

Inventor： Osamu Maeda

IPC: H05K116

CPC classification number: H05K1/184 ,  H05K3/301 ,  H05K3/366 ,  H05K7/12 ,  H05K2201/10643

Abstract: A part holder includes a part holding portion. In this part holding portion, a leadless part is held by a part receiving portion and an engaging piece. In such a state, the leadless part is inserted in a hole formed in a printed circuit board. At this time, a resilient piece provided on a leg of the part holder comes into abutment against an inner edge of the hole, whereby the part holder is fixed by the hole. Also, the part inserted in the hole is urged onto one surface of the hole by a resilient portion of the part holder. Thus, a pattern formed on one main surface of the part is closely contacted with a pattern formed on a backside of the printed circuit board.

Abstract translation: 部件保持器包括部件保持部。 在该部分保持部分中，无引线部分被部件接收部分和接合件保持。 在这种状态下，将无引线部分插入形成在印刷电路板上的孔中。 此时，设置在部件支架的腿部上的弹性件抵靠孔的内边缘，由此通过孔固定零件保持器。 此外，插入孔中的部分通过部件保持器的弹性部分被推压到孔的一个表面上。 因此，形成在该部件的一个主表面上的图案与形成在印刷电路板的背面上的图案紧密接触。

公开(公告)号：US06268078B1

公开(公告)日：2001-07-31

申请号：US09459226

申请日：1999-12-10

Applicant: Mark E. Tuttle

Inventor： Mark E. Tuttle

IPC: H01M642

CPC classification number: H01M2/1066 ,  H01M2/1044 ,  H01M2/204 ,  H01M6/42 ,  H02J7/0024 ,  H04B1/3883 ,  H05K3/321 ,  H05K2201/10037 ,  H05K2201/10515 ,  H05K2201/10643 ,  Y10T29/49108 ,  Y10T29/49114

Abstract: Thin-profile battery circuits and constructions, and in particular button-type battery circuits and constructions and methods of forming the same are described. In one implementation, a substrate is provided having an outer surface with a pair of spaced electrical contact pads thereon. At least two thin-profile batteries are conductively bonded together in a stack having a lowermost battery and an uppermost battery. The batteries include respective positive and negative terminals. The lowermost battery has one of its positive or negative terminals adhesively bonded to one of the pair of electrical contact pads while the uppermost battery has one of its positive or negative terminals electrically connected to the other of the pair of electrical contact pads. The batteries can be provided into parallel or series electrical connections.

Abstract translation: 描述了薄型电池电路和结构，特别是按钮式电池电路及其构成及其形成方法。 在一个实施方案中，提供了具有外表面的衬底，其上具有一对间隔的电接触焊盘。 至少两个薄型电池在具有最低电池和最上面的电池的堆叠中导电地结合在一起。 电池包括相应的正极和负极。 最下面的电池具有一个正极或负极端子，其粘合地粘合到一对电接触焊盘中的一个，而最上面的电池具有与该对电接触焊盘中的另一个电连接的正或负端子中的一个。 电池可以并联或串联电连接。