公开(公告)号：JPH03179942A

公开(公告)日：1991-08-05

申请号：JP29165090

申请日：1990-10-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SAFUDAA EMU ASUGAA ,  JIYON JII BAATOKOUIAKU

IPC: H03M1/66 ,  G06F17/17 ,  G06J1/00 ,  H04B14/04

Abstract: PURPOSE: To save labor for engineering setting and to attain its manufacturing by providing the device with a digital signal processing circuit for outputting an interpolated digital signal and constituting the digital signal processing circuit so as to allow a specified set of plural modules to repeat interpolation by the specified number of times. CONSTITUTION: A digital device 24 applies an outgoing digital signal to an interpolation circuit 18 through a line 26. The circuit 18 executes interpolating operation for the output digital signal received through the line 26 and outputs an interpolated digital signal to a digital/analog(D/A) circuit 14 through a line 28. The circuit 18 consists of an interpolator module 19 and an output circuit 92. An additional interpolator module 19a may be added to execute additional interpolation as necessity. The module 19 consists of a 1st digital circuit 68 and 2nd digital cell circuits 70, 72, 73. Second digital cell circuits may be added to the module 19 to execute interpolation of a larger degree as necessity.

公开(公告)号：JPH03105791A

公开(公告)日：1991-05-02

申请号：JP23690990

申请日：1990-09-05

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIMII FUAN ,  JIU AN ,  DEIBITSUDO ERU KIYANBURU ,  SUTEIIBUN SHIYUYU

IPC: G11C11/413 ,  G06F5/10 ,  G11C11/407 ,  G11C11/408 ,  G11C11/418 ,  H03K3/037

Abstract: PURPOSE: To allow a same circuit to be used both on a high power impression and a low power impression by providing a COMS(complimentary MOS) pipe line memory address buffer having a selective changeover means between an asynchronous operation and a synchronous operation of a buffer. CONSTITUTION: A buffer has a first and a second bus gates 21 and 22, and the bus gates 21 and 22 have individually a pair of complementary MOS(CMOS) transistors P21, N21 and P22, N22, and the buffer 20 is selectively changed over between the asynchronous mode and the synchronous mode in the operation. Further, this circuit is provided with a first means 31, 32 of alternately opening/closing the bus gates 21 and 22 when the buffer operates in synchronous mode, and a second means 33, 34 for simultaneously opening both bus gates 21 and 22 when the buffer operates in asynchronous mode. Consequently, a same circuit can be used both on high power impression and a low power impression.

公开(公告)号：JPH03102412A

公开(公告)日：1991-04-26

申请号：JP11966490

申请日：1990-05-08

Applicant: ADVANCED MICRO DEVICES INC

Inventor： UIRIAMU SHII PURANTSU

IPC: H01L27/04 ,  G05F3/24 ,  G05F3/26 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092

Abstract: PURPOSE: To reduce power consumption by fixing the voltage of a first source/ drain electrode of a first transistor to the threshold voltage of a first transistor. CONSTITUTION: Assuming that VGS16 is almost equal to VGS15 until the first order, that is, the source gate voltages of two transistors 15 and 16 are not substantially affected by the voltage of the substraight of an integrated circuit, VGS16 +VGS15 -VGS12 =VT, V20∼-VT. The voltage impressed on a current bias network 20 is substantially VT, and decided by a specific step used for manufacturing the integrated circuit. An output terminal connected with the source electrode of a transistor 12 is set as the threshold voltage of an NMOS transistor in the circuit. Moreover, the amounts of currents I1 biased by the network 20 are not considered for fixing the source electrode voltage of the VT Thus, power consumption can be reduced.

公开(公告)号：JPH0386991A

公开(公告)日：1991-04-11

申请号：JP18700690

申请日：1990-07-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUCHIYUAATO TEI OOBINEN ,  BARII EI HOBAAMAN

IPC: G11C11/401 ,  G06F5/00 ,  G11C7/10 ,  G11C11/409 ,  G11C11/419

Abstract: PURPOSE: To decrease a reading access time by arranging memory cells including sequential memory arrays in the plural odd numbered columns and the plural even numbered columns and connecting an output buffer with a detection means for generating data during an alternate reading cycle. CONSTITUTION: A sequential memory array 12 is comprised of plural memory cells, which are arranged in the plural odd numbered columns COL 1, COL 3 and the plural even numbered columns COL 2, COL 4. A detection means 10 is provided in order to interleave data stored in the memory cells in the odd numbered columns with those stored in the memory cells in the even numbered columns. An output buffer 16 is connected with the detection means 10 in order to generate output data which alternately represent the data stored in the odd and even numbered columns during the alternate reading cycle. Thus, since a reading mode is used on alternate cycles so as to be generated over a span of two cycles, the reading access time can be shorten.

公开(公告)号：JPH0320769B2

公开(公告)日：1991-03-20

申请号：JP50248782

申请日：1982-07-12

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MAGURINKII JERARUDO FURANSHISU

IPC: G05F1/56 ,  G05F3/16 ,  G05F3/20 ,  G05F3/30

公开(公告)号：JPH02294142A

公开(公告)日：1990-12-05

申请号：JP8059290

申请日：1990-03-28

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIIN GURAMUROOZU ,  JIYOO UIRIAMU PIITAASON

IPC: H04M1/00 ,  G06F1/32 ,  G06F13/24 ,  H04L29/08 ,  H04L29/12 ,  H04M1/253

Abstract: PURPOSE: To reduce power consumption by making a peripheral device speed up a clock signal to a microprocessor automatically when the peripheral device detects an event requiring service. CONSTITUTION: A microprocessor 10 reads in and writes in data to a peripheral device 12 including a clock divider 20 which is under the control of the peripheral device 12 as well as the microprocessor 10. The peripheral device 12 at the same time when an interruption to the microprocessor 10 occurs, for example, when a packet arrives from a central station, increases the speed of a clock to the microprocessor 10. The microprocessor uses the high-speed clock signal to process packets and instructs the peripheral device 12 to decrease the frequency to the lower than that of the clock so that electric power is not consumed thereafter. Consequently, the power consumption can be reduced.

公开(公告)号：JPH02262374A

公开(公告)日：1990-10-25

申请号：JP3506090

申请日：1990-02-15

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AN KEI UU

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/0812 ,  H03K17/16 ,  H01L29/784

Abstract: PURPOSE: To obtain a simple system at a reasonable manufacturing cost for protecting an electronic component by a method wherein a transmission gate possessed of a source and a drain as an input and an output respectively is connected to the input of a MOS component gate. CONSTITUTION: An electrostatic protective system is used together with a voltage-responsive MOS component 50 possessed of a gate input and provided with an oxide layer previously prescribed in thickness, wherein the protective system comprises the MOS component 50 provided with a gate input 52 and a transmission gate 54 possessed of a source and a drain as an input and an output respectively, and the transmission gate 54 is connected to the gate input 52 of the MOS component 50 so as to protect the MOS component 50 against discharge caused by a sudden electric voltage surge. For instance, the above transmission gate 54 comprises a thick oxide layer which is substantially thicker than the oxide layer of the gate input 52 of the MOS component 50. The above protective system comprises also a well-known ESD circuit 56.

公开(公告)号：JPH02246417A

公开(公告)日：1990-10-02

申请号：JP3505990

申请日：1990-02-15

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AN KEI UU

IPC: H03K5/151

Abstract: PURPOSE: To secure a more uniform pulse width in a clock phase at a high working frequency by providing two inverters and a NOR gate. CONSTITUTION: A NOR gate 46 and inverters 42 and 44 respectively have delaying functions and, when a clock signal becomes 'high', an inverted clock(CKB) 4 signal first becomes 'low' before an output clock(CK) becomes 'high', because the gate 46 is switched earlier than the inverters 42 and 44. When the clock signal becomes 'low', the CKB signal does not become 'high' until the CK signal becomes 'low', because the input to the gate 46 through a line 52 is not generated until both inverters 42 and 44 become active. Therefore, a circuit 40 operates with a shorter delay and a more uniform pulse width phase.

公开(公告)号：JPH02215228A

公开(公告)日：1990-08-28

申请号：JP32705789

申请日：1989-12-15

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MIKI TSUBI MOYARU

IPC: H03M1/38 ,  H03M1/00 ,  H03M3/02

Abstract: PURPOSE: To provide an analog/digital converter which is relatively insensitive to a noise by sampling an analog signal in a differential mode, and operating analog/digital conversion by providing a non-switch capacitance integrator in a specific design. CONSTITUTION: An analog signal is applied to a circuit 20 by a split input stage 25 equipped with two arithmetic amplifiers 26 and 27, an analog voltage input is received through a line 28, and this input is converted into a differential analog current signal by resistance R2 and R3. Those current signals are transmitted through lines 28 and 29 to an integrator input stage 30. Differential reference currents are applied from a DAC 35 with 6.02dB per bit through lines 31 and 32 to the integrator stage 30. The analog and reference currents are connected at nodes 33 and 34 of a dual common node feedback loop 36, and integrated by capacitors C1 and C2. The analog current signal is compared with the reference generated current signal by a comparator 40 so that the signal can be digitized.

公开(公告)号：JPH02181536A

公开(公告)日：1990-07-16

申请号：JP28982589

申请日：1989-11-07

Applicant: ADVANCED MICRO DEVICES INC

Inventor： KADEIREESAN ANNAMARAI

IPC: H04L29/02 ,  H04J3/06 ,  H04L7/04

Abstract: PURPOSE: To provide a synchronized token network system where bits of any information are not deleted by generating a clock signal and converting a digital signal in accordance with a preliminarily determined code to generate the start of a packet division and arranged synchronizing signals. CONSTITUTION: A means 60 which adjusts a synchronizing signal to respond to detection of the division for a preliminarily determined period is connected to a synchronizing signal generation means. A decoding and generation means 62 gives a decoded bit signal in response to the synchronizing signal and the converted serial digital signal. Consequently, any information is not deleted from an encoder/decoder(ENDEC) receiver.