公开(公告)号：EP1667004A3

公开(公告)日：2007-01-03

申请号：EP05111142.5

申请日：2005-11-23

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chatterjee, Kallol ,  Sreekiran, Samala

IPC: G05F3/24

CPC classification number: G05F3/242

Abstract: An improved first order temperature compensated reference current generator. It comprises a current device providing a controlled current, a startup circuit connected to said current device for initiating operation of said current device, and a current definition mechanism driven by said current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The said current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

公开(公告)号：EP1517335A3

公开(公告)日：2006-08-16

申请号：EP04018572.0

申请日：2004-08-05

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Ahmad, Nasim

IPC: G11C29/00

CPC classification number: G11C29/804 ,  G11C11/41 ,  G11C29/806

Abstract: The present invention relates to an improved semiconductor memory device providing row/column redundancy comprising a plurality of data latches (11) arranged in a row-column matrix connected to a set of bitlines / global bitlines interfacing to read/write circuitry, at least two redundant rows/columns (R1, R2) connected to a redundant bitline / global bitline, a first means (5) for providing a first faulty row/column address in the matrix, a second means (1, 16) for generating other faulty row/column addresses by incrementing or decrementing predetermined numbers from the address provided by the first means (5), a comparison circuitry (3, 13) receiving as its inputs the accessed row/column address and the faulty row/column addresses and a control block (4, 14) connected to the comparison circuitry (3, 13) and receiving a control signal (REN, CS) for normal operation of the memory device, the control block (4, 14) enabling/disabling the redundant rows/columns (R1, R2) and/or other memory cell rows/columns depending upon signals received from the comparison circuitry (3, 13) and the control signal (CS) for normal operation of the memory device.

公开(公告)号：EP1667009A1

公开(公告)日：2006-06-07

申请号：EP05111629.1

申请日：2005-12-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Jaisinghani, Pooja ,  Nandy, Tapas

IPC: G06F1/28 ,  G06F1/26 ,  G01R19/165 ,  G11C16/30

CPC classification number: G01R19/16576 ,  G01R19/16538 ,  Y10T307/735 ,  Y10T307/74

Abstract: The present invention provides a supply identifier, which takes precise decision on the range of the external supply to manage a proper internal supply to the core of the IC by controlling a regulator or a switch connected to external supply. This supply identifier, defers the decision till everything that influence the decision settles after power-up, then makes a decision only once depending on the external supply range and switches itself off keeping the decision stored, to avoid noise induced wrong behavior and to reduce power consumption.

Abstract translation: 本发明提供了一种电源识别器，其通过控制连接到外部电源的调节器或开关来精确决定外部电源的范围，以管理适当的IC内核电源。 这个电源标识符将延迟决定，直到决定了所有影响决定的决定，然后根据外部电源范围决定一次，并自行切换以保持决策存储，避免噪声导致的错误行为并降低功耗 消费。

公开(公告)号：EP1608178A1

公开(公告)日：2005-12-21

申请号：EP04291550.4

申请日：2004-06-18

Applicant: STMicroelectronics S.A. ,  STMicroelectronics Pvt. Ltd

Inventor： Gautier, Antoine ,  Chandra, Mahesh

IPC: H04N7/26 ,  H04N7/01

CPC classification number: H04N19/60 ,  H04N19/85 ,  H04N2201/33378

Abstract: The conversion device comprises an input for receiving data corresponding to an image to be displayed, said received data being in a JPEG decoder output data format and processing means for reconstructing and writing the image to be displayed into said image memory, in a display module expected input data format. The bandwidth of the image memory (MM) is greater than one byte. Said processing means are fully hardwired and comprises a first logic stage (LST1) for writing said received data byte by byte into an intermediate memory (ITM) at chosen addresses such that said written data form a sequence of data in said display module expected input data format, and a second logic stage (LST2) for reading said written data in said intermediate memory, forming successive packets of read data having a size corresponding to said bandwidth, and successively writing said packets into said image memory (MM) at chosen addresses such that said written packets form together all the lines of said image.

Abstract translation: 变换装置，用于接收数据对应于输入的图像包括要被显示的，所述所接收的在一个JPEG解码器输出数据格式的数据是与用于重建和写入图像处理装置要被显示到所述图像存储器，预期的显示模块中 输入数据格式。 图像存储器（MM）的带宽是大于一个字节。 所述处理装置是完全硬连线和包括第一逻辑级（LST-1）用于写入所述检查，所述写入的数据形成数据在所述显示模块预期的输入数据的顺序选择的地址接收到由字节数据字节到在中间存储器（ITM） 格式，以及用于读出所述写入数据在所述中间存储器，形成具有大小对应于所述的带宽，并且连续地在所选择的地址搜索写入所述数据包到所述图像存储器（MM）的读取数据的连续分组的第二逻辑级（LST2） 在于所述书面形式的数据包一起，所述图像的所有行。

公开(公告)号：EP1473644A3

公开(公告)日：2005-09-21

申请号：EP04009701.6

申请日：2004-04-23

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Sharma, Sunil Kumar ,  Tomar, Ajay ,  Samanta, Dhabalendu

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: The present invention provides an improved method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements comprising steps of, forming logic element groups including individual logic elements and/ or previously formed logic element groups that are capable of being accommodative with in the fanin and /or fanout capacity of a target LUT, mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner that at each stage only the unapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.

公开(公告)号：EP1538533A2

公开(公告)日：2005-06-08

申请号：EP04106295.1

申请日：2004-12-03

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Maiti, Srijib Narayan ,  Cornero, Marco

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: An improved FFT / IFFT processor comprising computation means capable of processing butterfly operations, and storage means for storing the operands of butterfly operations, and a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations, and wherein the computation means is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract translation: 一种改进的FFT / IFFT处理器，包括能够处理蝶形运算的计算装置和用于存储蝶形运算的操作数的存储装置，以及用于在连续的存储位置存储多个连续的蝶形运算的操作数的机构，并且其中计算装置能够 同时访问和处理所述多个蝴蝶操作。

公开(公告)号：EP1460640A3

公开(公告)日：2005-05-04

申请号：EP04006654.0

申请日：2004-03-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Srivastavaan, Rajeev ,  Grover, Chiranjeev

IPC: G11C15/04

CPC classification number: G11C15/00

Abstract: This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match.

公开(公告)号：EP1521187A1

公开(公告)日：2005-04-06

申请号：EP04104798.6

申请日：2004-09-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Goel, Ashish Kumar ,  Aggarwal, Davinder

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  H03K19/1776

Abstract: The present invention relates to a Programmable Logic Device providing efficient scalability for configuration memory programming while requiring reduced area for implementation, comprising: an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

Abstract translation: 本发明涉及一种可编程逻辑器件，其为配置存储器编程提供有效的可扩展性，同时需要减少实现的面积，其包括：配置存储器单元的阵列，连接到配置存储器阵列的垂直线的垂直移位寄存器（VSR） 单元，连接到配置存储单元阵列的水平线的选择寄存器（SR），提供对选择寄存器（SR）的使能输入的水平移位寄存器（HSR）以及同步的配置状态机（CSM） VSR，SR和HSR的操作。

公开(公告)号：EP1259079A3

公开(公告)日：2004-12-01

申请号：EP02008699.7

申请日：2002-04-18

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chelladurai, Paul, Sathya ,  Ahmed, Arshad ,  Nandy, Soumitra, Kumar

IPC: H04N7/26

CPC classification number: H04N19/53 ,  H04N19/14 ,  H04N19/194 ,  H04N19/61

Abstract: The present invention provides a system, method and computer program product for efficient low power motion estimation of a digital video image wherein processing requirements are reduced, the reduction being dependent on the content being processed. The method performs motion estimation of a current video image using a search window of previous video image. The method comprises as a first step the formation of the mean pyramids of the reference macroblock and the search area. This is followed by full search at the lowest resolution. The number of CMVs propagated to lower levels is dependent on the QADE of the current macroblock and the maximum distortion band obtained during training for that QADE value at that particular level. The process of training over a sequence is triggered at the beginning of every sequence. This training technique is required to determine the value of the maximum distortion band for all QADEs of the macroblocks, occurring over the training frames.

公开(公告)号：EP1473644A2

公开(公告)日：2004-11-03

申请号：EP04009701.6

申请日：2004-04-23

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Sharma, Sunil Kumar ,  Tomar, Ajay ,  Samanta, Dhabalendu

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: The present invention provides an improved method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements comprising steps of, forming logic element groups including individual logic elements and/ or previously formed logic element groups that are capable of being accommodative with in the fanin and /or fanout capacity of a target LUT, mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner that at each stage only the unapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.

Abstract translation: 对本发明的改进的方法提供了用于映射的逻辑电路，其包含的步骤可互相连接，可编程查找表（LUT）的元素的复数，形成逻辑元件组包括个别逻辑元件和/或先前形成的逻辑元件组也能够 为调节与所述扇入和/或所形成的逻辑元件群映射到所述目标LUT，并重复该过程以形成逻辑元件组和映射到目标的LUT用于以这样的方式在整个网络中的目标LUT的扇出能力做在 每个阶段仅unapped逻辑元件/元件和前级的映射逻辑元件组被认为是映射。