-
公开(公告)号：EP1873653A2
公开(公告)日：2008-01-02
申请号：EP07111349.2
申请日：1996-08-16
Applicant: MicroUnity Systems Engineering, Inc.
CPC classification number: G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.
-
公开(公告)号：EP1682861A1
公开(公告)日：2006-07-26
申请号：EP04795778.2
申请日：2004-10-20
Applicant: Aero Systems Engineering, Inc.
Inventor： LACEY, John, J., Jr.
IPC: G01M9/04
CPC classification number: G01M9/02 , G01M9/04 , H01L29/78391 , H01L29/792
Abstract: An open jet wind tunnel having a test section, a nozzle exit and a collector in which the leading edge of the collector is configured with at least a portion being non-uniformly spaced from the nozzle exit.
-
公开(公告)号：EP0902915A1
公开(公告)日：1999-03-24
申请号：EP97926582.0
申请日：1997-05-27
Applicant: Microunity Systems Engineering, Inc.
Inventor： CHEN, J., Fung
CPC classification number: G03F1/36 , G03F7/70433
Abstract: There is disclosed a photolithography mask and method of making the same that utilizes serifs to increase to correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of said optical exposure tool. About 33 to about 40 percent of the total surface area of the serifs overlap the corner regions of the mask.
-
公开(公告)号：EP0706731A1
公开(公告)日：1996-04-17
申请号：EP94921895.0
申请日：1994-05-02
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： MICHEL, Jean, Yves
IPC: H03M1
Abstract: A two-stage flash analog-to-digital signal converter is described. The first stage has a voltage divider network and a set of amplifiers that perform an initial interpolation. The initial interpolation results are directly coupled, i.e., no resistive or capacitive elements, to a second stage comprising a set of comparators having multiple inputs. The multiple inputs of the second stage comparators are weightily coupled to the first stage amplifiers in a manner so as to cause the second stage comparators to generate a digital representation of the analog signal.
-
公开(公告)号：EP0620931A1
公开(公告)日：1994-10-26
申请号：EP93903571.0
申请日：1993-01-15
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： CHEN, Jang, Fung , MATTHEWS, James, A.
CPC classification number: G03F1/36 , G03F7/70433 , G03F7/70441
Abstract: Est décrit un perfectionnement pour réduire les effets de proximité, consistant à ajouter, dans le motif de masque, des lignes minces appelées barres d'égalisation d'intensité. Ces barres d'égalisation ont pour fonction d'ajuster les gradients d'intensité des bords isolés du motif de masque, afin qu'ils correspondent aux gradients d'intensité des bords très rapprochés. Ces barres d'égalisation sont placées parallèlement aux bords isolés de telle manière que l'égalisation des gradients d'intensité s'effectue sur tous les bords isolés du motif de masque. En outre, les barres d'égalisation sont destinées à présenter une largeur notablement inférieure à la résolution de l'outil de sensibilisation. Par conséquent, lesdites barres qui sont présentes dans le motif de masque produisent des motifs de résist qui disparaissent complètement au dléveloppement lorsqu'une énergie de sensibilisation nominale est utilisée pendant l'exposition du photorésist.
-
Patent Agency Ranking
公开(公告)号：EP3276486A1
公开(公告)日：2018-01-31
申请号：EP17183101.9
申请日：2017-07-25
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： HANSEN, Craig , MOUSSOURIS, John , MASSALIN, Alexia
IPC: G06F7/544
CPC classification number: G06F7/523 , G06F7/5045 , G06F7/5443 , G06F2207/3828
Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations are disclosed.
Abstract translation: 公开了一种用于对需要大量乘法和累加的向量操作数执行外积和外积累积操作的处理器和方法。
-
127.发明授权
公开(公告)号：EP2829080B1
公开(公告)日：2017-08-16
申请号：EP13764677.4
申请日：2013-03-14
Applicant: Adamson Systems Engineering Inc.
Inventor： ADAMSON, Alan Brock , CABOT, Ben
CPC classification number: H04R3/12 , H02J7/00 , H02J9/06 , H04R3/00 , H04R27/00 , H04R29/007 , H04R2201/028 , H04R2227/003
-
公开(公告)号：EP2309382B1
公开(公告)日：2014-12-03
申请号：EP10179602.7
申请日：1999-08-24
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Hansen, Craig
CPC classification number: G06F9/30014 , G06F7/483 , G06F7/4991 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/30112 , G06F9/30167 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3885
Abstract: A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently by four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).
-
公开(公告)号：EP2284709B1
公开(公告)日：2014-11-26
申请号：EP10191073.5
申请日：2004-07-12
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Hansen, Craig , Moussouris, John , Massalin, Alexia
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.
-
公开(公告)号：EP2628311A1
公开(公告)日：2013-08-21
申请号：EP11831898.9
申请日：2011-10-13
Applicant: Adamson Systems Engineering Inc.
Inventor： ADAMSON, Alan Brock , CABOT, Ben , MCDONALD, Ewan James
Abstract: Disclosed herein is a rigging component and method for connecting an array element in an array. The rigging component includes an elongate housing connectable to an array element; a connection link disposed within, and slidably extendable from, one end of the housing; a conduit extending into the housing from its opposite end, the conduit dimensioned to receive another connection link extending from an adjacent rigging component; and at least one latching device associated with the conduit for releasably retaining the other connection link within the conduit. Further disclosed is a system for connecting an array element in an array. The system comprises at least one rigging component having a connection link extendable to be locked at a single fixed distance and at least one rigging component having a connection link extendable to be locked at one of a plurality of fixed distances.
-
-
-
-
-
-
-
-
-
Search Results
204
records
(took 0.034 seconds)
