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    TUNABLE RESONANT CIRCUIT IN AN INTEGRATED CIRCUIT
    123.
    发明申请
    TUNABLE RESONANT CIRCUIT IN AN INTEGRATED CIRCUIT 审中-公开
    集成电路中的可调谐谐振电路

    公开(公告)号：WO2012050676A1

    公开(公告)日：2012-04-19

    申请号：PCT/US2011/050048

    申请日：2011-08-31

    Applicant: XILINX. INC.

    Inventor： UPADHYAYA, Parag ,  KIREEV, Vassili

    IPC: H03B5/12

    CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1262 ,  H03B5/1265 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/0266

    Abstract: A tunable resonant circuit (102) includes first capacitors (104, 108, 216, 228, 232) and second capacitors (106, 1 10, 218, 230, 234) that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well (320, 326) disposed within a second well (322, 328) in a substrate (324). The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor (120, 130) are respectively coupled to the second electrode (1 14, 304) of the first capacitor and the second electrode (1 18, 308) of the second capacitor. Two channel electrodes of a second transistor (122, 132) are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor (124, 134) are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes (226, 314) of the first, second, and third transistors are responsive to a tuning signal (126, 136), and an inductor (144, 202) is coupled between the first electrodes (1 12, 1 16, 302, 306) of the first and second capacitors.

    Abstract translation: 可调谐谐振电路（102）包括在第一和第二电极之间提供匹配电容的第一电容器（104,108,216,228,232）和第二电容器（106,110,218,230,234） 第二电容器。 深井布置包括设置在衬底（324）中的第二阱（322,328）内的第一阱（320,326）。 第一和第二电容器各自设置在第一阱上。 第一晶体管（120,130）的两沟道电极分别耦合到第一电容器的第二电极（114）和第二电容器的第二电极（118,188）。 第二晶体管（122,132）的两沟道电极分别耦合到第一电容器的第二电极并接地。 第三晶体管（124,134）的两沟道电极分别耦合到第二电容器的第二电极并接地。 第一，第二和第三晶体管的栅极电极（226,314）对调谐信号（126,136）作出响应，并且电感器（144,202）耦合在第一电极（112,126， 302,306）的第一和第二电容器。

    INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN INTEGRATED CIRCUIT PACKAGE
    124.
    发明申请
    INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN INTEGRATED CIRCUIT PACKAGE 审中-公开

    公开(公告)号：WO2019067352A1

    公开(公告)日：2019-04-04

    申请号：PCT/US2018/052413

    申请日：2018-09-24

    Applicant: XILINX. INC.

    Inventor： LESEA, Austin H. ,  MOHAN, Sundararajarao ,  TRIMBERGER, Stephen M.

    IPC: G06F15/78

    Abstract: An example integrated circuit (IC) package includes: a processing system (104) and a programmable IC (106) disposed on a substrate (1 18), the processing system coupled to the programmable IC through interconnect (1 12) of the substrate; the processing system including components (202...208) coupled to a ring interconnect (210), the components including a processor (202) and an interface controller (214). The programmable IC includes: an interface endpoint (218) coupled to the interface controller through the interconnect; and at least one peripheral (230) coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

    PROTECTION OF A CIRCUIT DESIGN WITHIN A DESIGN CONTAINER
    125.
    发明申请
    PROTECTION OF A CIRCUIT DESIGN WITHIN A DESIGN CONTAINER 有权

    公开(公告)号：US20250156585A1

    公开(公告)日：2025-05-15

    申请号：US18505173

    申请日：2023-11-09

    Applicant: Xilinx, Inc.

    Inventor： Bin Dai Ochotta ,  Sudheendra Kusume ,  Alec J. Wong ,  Pradip K. Jha

    IPC: G06F21/72 ,  G06F30/392 ,  G06F115/08 ,  H04L9/08 ,  H04L9/14

    Abstract: A key block can be generated from a session key used by a computer-based design tool for a circuit design by encrypting the session key using computer hardware. The key block can be divided, by the computer hardware, into a plurality of sub-blocks. A plurality of enhanced sub-blocks can be generated by the computer hardware by encrypting each sub-block of the plurality of sub-blocks with a different key of a plurality of keys corresponding to a plurality of Intellectual Property (IP) cores of the circuit design. The plurality of enhanced sub-blocks can be stored in a memory.

    Mixed Sign Multiplier Devices and Methods
    126.
    发明申请
    Mixed Sign Multiplier Devices and Methods 有权

    公开(公告)号：US20250130770A1

    公开(公告)日：2025-04-24

    申请号：US18493233

    申请日：2023-10-24

    Applicant: Xilinx, Inc.

    Inventor： Chinmaya Dash

    IPC: G06F7/523 ,  G06F5/01 ,  G06F7/50 ,  H03K19/21

    Abstract: An implementation may include a method for performing a binary multiplication including receiving a first at an input interface of a digital multiplier circuit in the computing system, receiving a second operand at the input interface of the digital multiplier circuit, generating, by the digital multiplier circuit, partial products by performing a AND operation with each of the N bits of the first operand and each of the bits of the second operand, and generating first modified partial products by modifying, by the digital multiplier circuit, most significant bits of the partial products, generating second modified partial products by modifying, by the digital multiplier circuit, one of the first modified partial product, generating, by the digital multiplier circuit, a product by summing the second modified partial products, and outputting the product from an output interface of the digital multiplier circuit.

    EFFICIENT METHOD FOR THE LATCH TIMING ANALYSIS OF ELECTRONIC DESIGNS
    127.
    发明申请
    EFFICIENT METHOD FOR THE LATCH TIMING ANALYSIS OF ELECTRONIC DESIGNS 有权

    公开(公告)号：US20250124204A1

    公开(公告)日：2025-04-17

    申请号：US18381052

    申请日：2023-10-17

    Applicant: XILINX, INC.

    Inventor： Pawan KULSHRESHTHA ,  Atul SRINIVASAN

    IPC: G06F30/3312 ,  G06F30/31

    Abstract: Performing timing analysis of a circuit design includes building a timing graph of the circuit design, and determining delays of devices and wires of the circuit design based on the timing graph. Further, clock and arrival propagations for the circuit design are performed based on the delays of the devices and wires, latch loops are identified in the circuit design, and latch analysis on latches of the latch loops is performed. The timing analysis further includes performing arrival propagation for circuit elements of the circuit design impacted by the latch analysis performed on the latches of the latch loops, performing latch analysis on latches of the circuit design external to the latch loops, and performing required time and slack calculations on the circuit design.

    RANDOMIZATION OF INSTRUCTION EXECUTION FLOW FOR GLITCH PROTECTION
    129.
    发明申请
    RANDOMIZATION OF INSTRUCTION EXECUTION FLOW FOR GLITCH PROTECTION 有权

    公开(公告)号：US20250077243A1

    公开(公告)日：2025-03-06

    申请号：US18242246

    申请日：2023-09-05

    Applicant: XILINX, INC.

    Inventor： Mohan Marutirao DHANAWADE ,  Ramakrishna Ganeshu POOLLA ,  Ahmad R. ANSARI

    IPC: G06F9/448

    Abstract: Some examples described herein provide for instruction glitch protection in an integrated circuit. In an example, a method includes generating a random number by the integrated circuit. The method also includes identifying, based at least in part on the generated random number, a sequence from a set of sequences stored in a memory of the integrated circuit, each sequence of the set of sequences corresponding to an order of execution for a plurality of tasks. The method further includes performing, by the integrated circuit, each task of the plurality of tasks in the order of execution corresponding to the identified sequence.

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