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公开(公告)号：KR1019970006742B1
公开(公告)日：1997-04-29
申请号：KR1019930028481
申请日：1993-12-18
Applicant: 한국전자통신연구원
IPC: H01L29/84
Abstract: A method is described that uses a substrate joining technique and anisotropic etching characteristic of a silicon substrate to fabricate the detection part of a pressure sensor. The method includes of the steps of joining two substrates 201 and 202 having a crystal direction different from each other via an oxide layer 202, making one of the substrates 201 and 202 be the thin film having a thickness of a diaphram 207, forming a pressure receiving part 205 at a desired portion of the the substrates 201 using selective anisotropic etching, and etching the substrates 201 to form a space region 206 between the the substrates 201 and diaphram 207. Thereby, it is possible to form the detection part having a wider section area of diaphram 207 than that of the pressure receiving part 205.
Abstract translation: 描述了使用硅衬底的衬底接合技术和各向异性蚀刻特性来制造压力传感器的检测部分的方法。 该方法包括通过氧化物层202将具有彼此不同的晶体方向的两个基板201和202接合的步骤，使得基板201和202中的一个成为厚度为20μm的薄膜，形成压力 使用选择性各向异性蚀刻在基板201的期望部分处接收部分205，并且蚀刻基板201以在基板201和二角膜207之间形成空间区域206.由此，可以形成具有更宽的检测部分 堤面207的剖面面积大于受压部分205的截面面积。
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公开(公告)号：KR1019970004214B1
公开(公告)日：1997-03-26
申请号：KR1019930029625
申请日：1993-12-24
Applicant: 한국전자통신연구원
IPC: H01H59/00
Abstract: The micro relay for operating with low voltage less than 10 V has rapid response speed less than 100 micro second. The relay has a cantilever shape thin metal electrode on SiO2 insulator. The gap between electrodes is less than 2 micro meter to be driven with low voltage. It also uses liquified mercury as upper cover plate to maintain low contact resistance and prolong operation time.
Abstract translation: 用于低于10 V低电压工作的微型继电器，响应速度快于100微秒。 继电器在SiO2绝缘体上具有悬臂形薄金属电极。 电极之间的间隙小于2微米，以低电压驱动。 它还使用液化汞作为上盖板，以保持低接触电阻并延长操作时间。
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Patent Agency Ranking
公开(公告)号：KR1019950000138B1
公开(公告)日：1995-01-10
申请号：KR1019910024519
申请日：1991-12-26
IPC: H01L29/68
Abstract: forming an Si collector layer (31,32) and an insulating film (33) pattern on a P type semiconductor substrate (30) to implant impurities thereinto to form a collector connection part (34); growing a base crystal film (35) on an active region; forming insulating films (36,37), a poly-Si film (38), an insulating film (39) and a poly-Si film (40) thereon to etch the films (37,38,39,40) to form double side insulating films (41,42); depositing a poly-Si film (43) for a base electrode; flattening the film (43) to expose the film (39) on the poly-Si film (38); and forming emitter and collector regions and a metallic electrode; thereby forming the double side insulating films (41,42) to self-align the emitter and base regions to reduce parasitic resistance.
Abstract translation: 在P型半导体衬底（30）上形成Si集电极层（31,32）和绝缘膜（33）图案以将杂质注入其中以形成集电器连接部分（34）; 在活性区域上生长基底晶体膜（35）; 在其上形成绝缘膜（36,37），多晶硅膜（38），绝缘膜（39）和多晶硅膜（40），以蚀刻膜（37,38,39,40）以形成双 侧绝缘膜（41,42）; 沉积用于基极的多晶硅膜（43）; 使膜（43）变平，使多晶硅膜（38）上的膜（39）露出; 并形成发射极和集电极区域和金属电极; 从而形成双面绝缘膜（41,42）以自发对准发射极和基极区域以减小寄生电阻。
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公开(公告)号：KR1019950002055A
公开(公告)日：1995-01-04
申请号：KR1019930012202
申请日：1993-06-30
IPC: H01L29/73
Abstract: 본 발명은 컴퓨터 통신기기 등 차세대 고속정보처리 시스템에 있는 고속 쌍극자 트랜지스터의 제조방법에 관한 것으로, 실리사이드(2-5)를 형성하고 절연막(2-6)과 마스킹 절연막을 도포한 다음 식각하였으며 이후에 마스킹 절연막을 다시 도포하고 비등방성 식각으로 마스킹 절연막의 측면절연막을 형성하고 실리사이드를 선택적 습식식각으로 제거하여 절연막(2-6)과 베이스(2-4)에 손상을 주지않으면서 에미터영역을 형성하였다. 그리고 마스킹 절연막을 제거하고 에미터다결정 규소층(2-8)과 베이스전극용 실리사이드(2-8)를 도포하고 식각으로 정의하여 에미터층을 형성하였다.
다음으로 보호막(2-9)을 도포하고 식각하여 금속(2-10) 접촉을 형성하여 금속을식각으로 정의한다.
종래의 기술에 비하여 베이스 저항이 현저히 감소하며 매우 간단하고 신뢰성이 있는 공정을 사용하였으므로 제조공정의 재현성을 크게 증가시켰다.-
公开(公告)号：KR1019940010915B1
公开(公告)日：1994-11-19
申请号：KR1019910024260
申请日：1991-12-24
IPC: H01L29/68
Abstract: The method includes the steps of forming Si thin films (41,42) on an Si substrate (40) to form a connection portion (43) for the metallic contact of collector by using the impurity ion implantation, forming a trench (44) thereinto, applying an insulating film (45), poly-Si layer (46) and an insulating film (47) sequentially onto the layer (42), etching the films (47,46) an isotropically and the film (45) isotropically to form an active region, forming a poly-Si layer (49), forming a base (50) and a base layer (46), forming and etching an insulating film to define an emitter, removing the insulating film to form a poly-Si emitter (53) and a poly-Si collector (54), and spattering and etching an insulating film (55) thereonto to form metallic wirings (56), thereby increasing the contact area between the poly-Si regions for base electrodes to reduce the parasitic resistance.
Abstract translation: 该方法包括以下步骤：在Si衬底（40）上形成Si薄膜（41,42），以通过使用杂质离子注入形成用于集电器的金属接触的连接部分（43），在其中形成沟槽（44） ，将绝缘膜（45），多晶硅层（46）和绝缘膜（47）顺序地施加到层（42）上，各向同性地蚀刻膜（47,46），并且各向同性地形成膜（45）以形成 有源区，形成多晶硅层（49），形成基极（50）和基极层（46），形成和蚀刻绝缘膜以限定发射极，去除绝缘膜以形成多晶硅发射极 （53）和多晶硅集电体（54），并在其上溅射和蚀刻绝缘膜（55）以形成金属布线（56），从而增加用于基底电极的多晶硅区域之间的接触面积，以减少寄生 抵抗性。
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公开(公告)号：KR1019940010566B1
公开(公告)日：1994-10-24
申请号：KR1019910018984
申请日：1991-10-28
Applicant: 한국전자통신연구원
IPC: H01L21/335 , H01L27/12
Abstract: The pseudo-SOI semiconductor device includes a holding substrate (8) joined to a seed substrate (1), an Si insulating layer (9) formed on the substrate (8), an electrode layer (10) formed on the layer (9), and an active region having an insulating layer (12) formed by a LOCOS and channels (13a,13b). The channels of the active region are in contact with the electrode layer (10) directly, thereby applying the sub-potential to the channels. The insulation layer (11) is formed between the electrode layer (10) and the source (16a) and drain (16b) of the active region. Thereby, the device has a high device isolation ability and a reduced parasitic junction capacitance.
Abstract translation: 伪SOI半导体器件包括接合到种子基板（1）的保持基板（8），形成在基板（8）上的Si绝缘层（9），形成在层（9）上的电极层（10） 以及具有由LOCOS和通道（13a，13b）形成的绝缘层（12）的有源区。 有源区的沟道直接与电极层（10）接触，从而将子电位施加到通道。 绝缘层（11）形成在有源区的电极层（10）与源极（16a）和漏极（16b）之间。 因此，器件具有高的器件隔离能力和降低的寄生结电容。
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公开(公告)号：KR1019940010517B1
公开(公告)日：1994-10-24
申请号：KR1019910021084
申请日：1991-11-25
IPC: H01L21/328
Abstract: The method provides a high-speed bipolar device which is useful in computers, communication and high-speed information systems. The method comprises the step of: defining electrodes (7,8,9) emitter, base and collector contacts by a trench-etching method and isolating them with oxide film (13), doing independently impurity doping in inactive (12) and active (14) regions by applying BSG oxide film (2) to the single polycrystalline silicon layer (1) accumulating nitrate film (3) as well as polycrystalline silicon film and stripping chemically side nitrate film (3) for controlling easily etching end-point, protecting BSG oxide film (2).
Abstract translation: 该方法提供了一种在计算机，通信和高速信息系统中有用的高速双极器件。 该方法包括以下步骤：通过沟槽蚀刻方法限定电极（7,8,9）发射极，基极和集电极触点，并用氧化物膜（13）分离它们，独立地进行杂质掺杂在非活性（12）和活性（ 通过将BSG氧化物膜（2）施加到积聚硝酸盐膜（3）的单个多晶硅层（1）以及多晶硅膜和剥离化学侧硝酸盐膜（3）上以控制容易蚀刻终点，保护 BSG氧化膜（2）。
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