公开(公告)号：DE112015000203T5

公开(公告)日：2016-09-01

申请号：DE112015000203

申请日：2015-02-23

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SCHMIDT DONALD WILLIAM ,  MITRAN MARCEL ,  GAINEY CHARLES JR

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: Bereitgestellt wird eine Verzögerungseinrichtung, in der eine Programmausführung verzögert werden kann, bis ein vordefiniertes Ereignis eintritt, z. B. bis ein Vergleich von Arbeitsspeicherpositionen eine wahre Bedingung ergibt, eine Zeitüberschreitung erreicht wird, eine Unterbrechung ausgesetzt wird oder eine andere Bedingung gegeben ist. Die Verzögerungseinrichtung beinhaltet einen oder mehrere „Compare and Delay”-Maschinenbefehle, mit denen eine Ausführung verzögert wird. Der eine oder die mehreren „Compare and Delay”-Befehle können einen 32-Bit-„Compare and Delay”-Befehl (CAD-Befehl) und einen 64-Bit-„Compare and Delay”-Befehl (CADG-Befehl) beinhalten.

公开(公告)号：AU2013276800B2

公开(公告)日：2016-08-18

申请号：AU2013276800

申请日：2013-05-03

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F11/36 ,  G06F9/46

Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.

公开(公告)号：AU2012382778B2

公开(公告)日：2016-08-18

申请号：AU2012382778

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F13/40 ,  G06F9/308 ,  G06F9/312

Abstract: A transaction begin instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

公开(公告)号：AU2015238632A1

公开(公告)日：2016-08-04

申请号：AU2015238632

申请日：2015-03-19

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES ,  JACOBI CHRISTIAN

IPC: G06F9/50 ,  G06F9/38

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

公开(公告)号：AU2013276133B2

公开(公告)日：2016-06-30

申请号：AU2013276133

申请日：2013-06-12

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F9/46

Abstract: A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.

公开(公告)号：AU2012382780B2

公开(公告)日：2016-06-23

申请号：AU2012382780

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  RELSON PETER JEREMY ,  PHILLEY RANDALL WILLIAM

IPC: G06F12/00

Abstract: An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.

公开(公告)号：AU2012373734B2

公开(公告)日：2016-06-02

申请号：AU2012373734

申请日：2012-11-15

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL ,  SLEGEL TIMOTHY ,  SCHWARZ ERIC MARK ,  JACOBI CHRISTIAN

IPC: G06F12/10

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.

公开(公告)号：GB2528901A

公开(公告)日：2016-02-10

申请号：GB201413750

申请日：2014-08-04

Applicant: IBM

Inventor： BRANDT UWE ,  RECKTENWALD MARTIN ,  JACOBI CHRISTIAN ,  BILLECI MICHAEL

IPC: G06F11/07

Abstract: Performing an error recovery in response to determining an uncorrectable error in data stored in the memory system, storing the address of a memory location of the uncorrectable error in an address buffer and performing a recovery procedure for the processor core which may reset the processor core to a known status with correct data. When fetching data from a memory location and if it is determined that the address of this memory location is stored in the address buffer, moving the content of an entire cache line related to the address into a quarantine buffer of the processor core. When detecting an error in the data of the moved entire cache line, triggering a repair procedure for the data of this address which may be a special procedure to repair unrecoverable detected errors in data to be processed by a processor core.

公开(公告)号：CA2940915A1

公开(公告)日：2015-09-17

申请号：CA2940915

申请日：2015-03-11

Applicant: IBM

Inventor： SCHWARZ ERIC MARK ,  BUSABA FADI YUSUF ,  GSCHWIND MICHAEL KARL ,  SLEGEL TIMOTHY ,  SALAPURA VALENTINA ,  JACOBI CHRISTIAN ,  CAIN HAROLD WADE III

IPC: G06F9/46 ,  G06F12/0815

Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

公开(公告)号：GB2520942A

公开(公告)日：2015-06-10

申请号：GB201321307

申请日：2013-12-03

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  PFLANZ MATTHIAS ,  WEBBER KAI ,  SCHUH STEFAN ,  DITTRICH JENS

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0882

Abstract: Disclosed is a multi-processor system 1 with a multi-level cache L1, L2, L3, L4 structure between the processors 10, 20, 30 and the main memory 60. The memories of at least one of the cache levels is shared between the processors. A page mover 50 is positioned closer to the main memory and is connected to the cache memories of the shared cache level, to the main memory and to the processors. In response to a request from a processor the page mover fetches data of a storage area line-wise from one of the shared cache memories or the main memory, while maintaining cache memory access coherency. The page mover has a data processing engine that performs aggregation and filtering of the fetched data. The page mover moves processed data to the cache memories, the main memory or the requesting processor. The data processing engine may have a filter engine that filters data by comparing all elements of a fetched line from a source address of a fetched line from a source address of the shared cache level or main memory with filter arguments to create a bitmask buffer of the target storage area.