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    121.
    发明专利
    未知

    公开(公告)号：AT491178T

    公开(公告)日：2010-12-15

    申请号：AT05108510

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F9/312 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

    Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

    122.
    发明专利
    未知

    公开(公告)号：DE602004008933D1

    公开(公告)日：2007-10-25

    申请号：DE602004008933

    申请日：2004-04-30

    Applicant: IBM

    Inventor： CHECK MARK ,  SLEGEL TIMOTHY ,  MOORE BRIAN

    IPC: G06F9/355 ,  G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F21/00 ,  H04L9/32

    Abstract: A method, system and computer program product for computing a message authentication code for data in storage of a computing environment. An instruction specifies a unit of storage for which an authentication code is to be computed. An computing operation computes an authentication code for the unit of storage.

    123.
    发明专利
    未知

    公开(公告)号：AT373264T

    公开(公告)日：2007-09-15

    申请号：AT05108499

    申请日：2004-04-30

    Applicant: IBM

    Inventor： CHECK MARK ,  SLEGEL TIMOTHY ,  MOORE BRIAN

    IPC: G06F9/355 ,  G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F21/00 ,  H04L9/32

    Abstract: A method, system and computer program product for computing a message authentication code for data in storage of a computing environment. An instruction specifies a unit of storage for which an authentication code is to be computed. An computing operation computes an authentication code for the unit of storage.

    Instrucción de carga lógica y desplazamiento protegido
    127.
    发明专利
    Instrucción de carga lógica y desplazamiento protegido 未知

    公开(公告)号：ES2893925T3

    公开(公告)日：2022-02-10

    申请号：ES18700180

    申请日：2018-01-03

    Applicant: IBM

    Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SAPORITO ANTHONY ,  PAPROTSKI VOLODYMYR ,  MITRAN MARCEL

    IPC: G06F9/30

    Abstract: Un producto de programa informático para facilitar el procesamiento en un entorno informático, comprendiendo dicho producto de programa informático: un medio de almacenamiento legible por ordenador que almacena instrucciones y legible por un circuito de procesamiento para: obtener una instrucción de Carga Lógica y Desplazamiento Protegido 'LLSG' para realizar una operación de carga y desplazamiento; y ejecutar la instrucción LLSG, comprendiendo la ejecución: cargar datos desde una ubicación en memoria, estando la ubicación en memoria designada por uno o más campos asociados a la instrucción; desplazar los datos en una cantidad de desplazamiento para obtener un valor desplazado; obtener un resultado intermedio usando el valor desplazado; y reconocer la aparición de un evento de almacenamiento protegido que comprende: usar el resultado intermedio para determinar si la instrucción designa una sección protegida de almacenamiento definida por un límite que indica un intervalo de direcciones que están protegidas, en el que en base a determinar que la instrucción designa la sección protegida de almacenamiento, el resultado intermedio no se carga en un registro especificado usando la instrucción LLSG; en cambio, se inserta en un registro de evento de almacenamiento protegido junto con los datos y la dirección de la instrucción LLSG que causa el evento de almacenamiento protegido.

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