公开(公告)号：JPH07154644A

公开(公告)日：1995-06-16

申请号：JP21943494

申请日：1994-08-22

Applicant: SONY CORP

Inventor： MOTOMIYA MASAYUKI ,  TAMURA TAKAHIKO ,  TOKUHARA MASAHARU

IPC: H04N5/16

Abstract: PURPOSE:To avoid a change in a brightness level or a color tone of a video image due to a black level reproduction by applying amplitude control to a black signal whose level is below a predetermined level of an input video signal and adding an original input signal and a black signal subjected to amplitude control to reproduce a black level, thereby avoiding black level deformation with proper black level extension. CONSTITUTION:A black level detection circuit 2 detects a black level signal whose level is below a predetermined level of an input video signal and the level of the extracted black level signal is controlled by a gain control amplifier 3 and the input video signal and an output of the gain control amplifier 3 are added by an adder 8. A black level peak detection circuit 5 detects a black peak level of an output video signal obtained from an output of the adder 8, the detected black peak level and a pedestal level of the output video signal are compared by a comparator circuit 6 and a comparison output is given to the gain control amplifier 3 as a gain control signal to obtain the output video signal whose black level is extended from the adder 8.

公开(公告)号：JPH0527311B2

公开(公告)日：1993-04-20

申请号：JP18352683

申请日：1983-09-30

Applicant: SONY CORP

Inventor： TOKUHARA MASAHARU ,  TAMURA TAKAHIKO ,  TOYODA NAOKUNI ,  KUEDA SHINJI

IPC: H04N9/73

公开(公告)号：JPH0518307B2

公开(公告)日：1993-03-11

申请号：JP15524983

申请日：1983-08-25

Applicant: SONY CORP

Inventor： MOTOMYA MASAYUKI ,  TAMURA TAKAHIKO ,  TOKUHARA MASAHARU

IPC: H04N5/18

公开(公告)号：JPH0462207B2

公开(公告)日：1992-10-05

申请号：JP16226183

申请日：1983-09-03

Applicant: SONY CORP

Inventor： MOTOMYA MASAYUKI ,  TAMURA TAKAHIKO ,  TOKUHARA MASAHARU

IPC: H03F3/00 ,  H03G1/00 ,  H03G3/10

公开(公告)号：JPH0452474B2

公开(公告)日：1992-08-21

申请号：JP20261782

申请日：1982-11-18

Applicant: SONY CORP

Inventor： IKEGAMI HIROICHI ,  KUME TSUTOMU ,  TOKUHARA MASAHARU

IPC: H04N9/64 ,  G09G1/00 ,  G09G1/28 ,  G09G5/00 ,  G09G5/04 ,  H04N9/68

公开(公告)号：JPH04157886A

公开(公告)日：1992-05-29

申请号：JP28368690

申请日：1990-10-22

Applicant: SONY CORP

Inventor： KAWASHIMA HIROYUKI ,  KITA HIROYUKI ,  OHANA SHUICHI ,  TOKUHARA MASAHARU

IPC: H04N5/46 ,  H04N7/01 ,  H04N9/64

Abstract: PURPOSE:To reduce disturbance generated in an interlace scan, for instance, the deterioration of a picture quality, etc., by executing an inter-field interpolation and an in-field interpolation in accordance with a motion detection of plural kinds of television signals which are inputted, and executing successively a scanning conversion. CONSTITUTION:A weighting addition block 13 performs weighting to an output signal. from a field memory 2 being an inter-field interpolating means and an output signal from an in-field interpolation forming block 10, respectively and adds them in accordance with an output signal from a motion detector 4, and forms an interpolation line. Based on an input video signal and an interpolation line signal from the block 13, a double speed converter scans alternately the line of the input video signal and an interpolation line at a doubl speed and converts it to a non-interlace scan. By this non-interlace scan, the number of lines becomes two folds. Accordingly, a Kel factor being a man's vision factor can also be improved, and deterioration of vertical resolution is improved remarkably.

公开(公告)号：JPH0432385A

公开(公告)日：1992-02-04

申请号：JP13708190

申请日：1990-05-29

Applicant: SONY CORP

Inventor： TOKUHARA MASAHARU ,  TOYODA NAOKUNI ,  KITA HIROYUKI

IPC: H04N9/00 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08

Abstract: PURPOSE:To eliminate a delay time difference in a comb-line filter by inputting a signal not Y/C separation at a Y/C separator circuit, that is, a composite video signal in a vertical blanking period to a text decoder. CONSTITUTION:Line subtraction processing by an arithmetic circuit 14 in a Y/C separator circuit 11 is not implemented during a vertical blanking period. Thus, a test data superimposed during the vertical blanking period of a composite video signal is not changed but outputted from the Y/C separation circuit 11. Thus, when a text decoder 17 extracts a text data from an output of the arithmetic circuit 14, proper decoding is attained. Since the text data passes through the Y/C separation circuit 11, the delay time difference between Y and C signals due to the characteristic of a comb-line filter is not generated naturally. Thus, the time difference due to the comb-line filter is very easily eliminated in a video signal and a text signal.

公开(公告)号：JPH0230204B2

公开(公告)日：1990-07-05

申请号：JP3513480

申请日：1980-03-19

Applicant: SONY CORP

Inventor： TSUCHA TAKAHISA ,  SONEDA MITSUO ,  NAKAMURA ISA ,  TOKUHARA MASAHARU ,  KITA HIROYUKI

IPC: G11C27/04 ,  G11C19/18 ,  H01L21/339 ,  H01L21/822 ,  H01L27/04 ,  H01L29/762 ,  H03H11/26 ,  H03H15/02 ,  H04N5/30

公开(公告)号：JPH02174488A

公开(公告)日：1990-07-05

申请号：JP33013388

申请日：1988-12-27

Applicant: SONY CORP

Inventor： NAITO HIDEFUMI ,  SARUGAKU TOSHIO ,  TOKUHARA MASAHARU

IPC: H04N11/04

Abstract: PURPOSE:To simply cope with the decision of a clock phase by providing a means selecting a clock frequency and extracting an output signal of an analog digital conversion circuit at either the rising or a falling of the clock. CONSTITUTION:A clock obtained at output terminals QA, QB, and QC of a counter 4 is switched by a changeover switch 5. An output of the switch 5 is fed to a changeover switch 6 via an inverter circuit 7. A clock phase decision means 2 throws a changeover switch 6 to the position of 6c-6a when an output signal of an A/D conversion circuit is obtained at the rising of the clock, and the clock phase decision means 2 throws the changeover switch 6 to the position of 6c-6b when an output signal of the A/D conversion circuit is obtained at the falling of the clock. The connection of fixed contacts 9a, 9b, 9c is decided depending whether the point of time of the output of the digital signal of the A/D conversion circuit is at the rising or the falling of the control clock.

公开(公告)号：JPH02162969A

公开(公告)日：1990-06-22

申请号：JP31827488

申请日：1988-12-16

Applicant: SONY CORP

Inventor： HOSHINO TAKANARI ,  TOKUHARA MASAHARU

IPC: H04N5/208

Abstract: PURPOSE:To adjust a correction quantity of a changing part of an original signal by adding or subtracting the original signal and output signal of 1st and 2nd delay means for the original signal and calculating further a contour correction signal. CONSTITUTION:The circuit is provided with a 1st delay means 2A retarding an original signal A, a 2nd delay means 2B retarding an output signal B of the 1st delay means 2A, adder and subtractor circuits 3, 4, 5 adding and substracting the original signal A and output signals B, C of the 1st and 2nd delay means to form 1st, 2nd and 3rd contour correction signals such as B-A, B-C and 2B-(A+C), and a logic arithmetic circuit 6 forming a 4th contour correction signal W from 1st, 2nd and 3rd contour correction signals. A signal KXW being a result of adjusting the gain of the 4th contour correction signal W and the output signal B of the 1st delay means 2A are added to correct a changing part of the original signal A.