公开(公告)号：WO0074932A9

公开(公告)日：2002-04-18

申请号：PCT/US0014862

申请日：2000-05-30

Applicant: PENN STATE RES FOUND ,  FONASH STEPHEN J ,  KALKAN ALI KAAN ,  BAE SANGHOON

Inventor： FONASH STEPHEN J ,  KALKAN ALI KAAN ,  BAE SANGHOON

IPC: B81B3/00 ,  B81C1/00 ,  C23C16/24 ,  C23C16/511 ,  G01N21/17 ,  G01N27/12 ,  G01N27/447 ,  H01J49/04 ,  H01J49/16 ,  B32B3/10 ,  C23C10/06 ,  C23C16/06 ,  H05H1/02

CPC classification number: B81C1/0038 ,  B81C1/00047 ,  B81C2201/0115 ,  B81C2201/0139 ,  B81C2201/018 ,  C23C16/24 ,  C23C16/511 ,  G01N21/17 ,  G01N27/121 ,  G01N27/44717 ,  G01N30/6095 ,  H01J49/0418 ,  Y10T428/24174 ,  Y10T428/249953

Abstract: A novel porous film (3) is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250 DEG C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90 %. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates (5).

Abstract translation: 公开了一种新颖的多孔膜（3），其包括连续空隙中的硅柱网络，其可以在低温即低于约250℃下使用高密度等离子体沉积来制造。该硅膜是二维纳米 棒状列的尺寸排列。 这种空隙柱形态可以用沉积条件控制，并且孔隙率可以变化高达90％。 在所采用的等离子体方法中同时使用低温沉积和蚀刻允许在同时获得柱状结构，连续空隙和多晶柱组成的独特机会。 可以使用该多孔连续膜通过将该膜等离子体沉积在玻璃，金属箔，绝缘体或塑料基底（5）上来制造独特的装置。

公开(公告)号：WO01046066A2

公开(公告)日：2001-06-28

申请号：PCT/DE2000/004454

申请日：2000-12-14

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  B81C5/00

CPC classification number: B81C1/00293 ,  B81B2201/0228 ,  B81B2207/095 ,  B81C2201/0115 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: According to the invention, the cover (13) of the inventive sensor is made of a first layer (32) (deposition layer) which is transparent to an etching to reaction products and has a hermetically sealed second layer (34) (sealing layer) located thereover. In the method according to the invention, at least the sensor chamber (28) is located in the base wafer (11) is filled with an oxide (30), in particular CVD oxide or porous oxide after a structure (26) has been established. The sensor chamber (28)is covered with a first layer (32) in particular a polysilicon layer which is or has been made transparent to the etching medium and the reaction products (deposition layer). The oxide (30) in the sensor chamber (28) is removed by an etching medium which etches through the deposition layer (32). A second layer (34) (sealing layer) is subsequently applied to the deposition layer (32) which hermetically seals the sensor chamber (28). Said second layer is in particular made of a metal or an insulator.

Abstract translation: 本发明涉及与至少一个微机械结构的传感器基于硅，其被集成到基底晶片的传感器区域，并且在覆盖传感器空间覆盖的区域和用于制造传感器的方法中的基底晶片的至少其中之一。 据设想，在本发明的传感器，由透明的盖（13）的蚀刻介质和反应产物中的第一层（32）（分离层）和上覆的气密地密封的第二层（34）（密封层），并且本发明的方法 至少在基底晶片（11）建立结构之后（26），现有的传感器腔室（28）填充有具有氧化物（30），特别是CVD氧化物或多孔氧化物，所述传感器室（28），一个用于蚀刻介质和反应产物 透明或随后作出透明的第一层（32）（分离层），特别是多晶硅，被覆盖，这是在所述传感器室（28）通过所述分离层（32）的氧化物（30）通过蚀刻介质和随后的第二层（去世 由金属或绝缘体（在沉积层32上）的34）（密封层），特别是施加到浅草 rraum（28）气密地密封。

公开(公告)号：US09988263B2

公开(公告)日：2018-06-05

申请号：US14914215

申请日：2013-08-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Patrick Wayne Sadik ,  Roger A. McKay

IPC: H01L21/306 ,  B81C1/00 ,  B41J2/16

CPC classification number: B81C1/00063 ,  B41J2/162 ,  B41J2/1626 ,  B81B2201/052 ,  B81C2201/0115 ,  B81C2201/0133 ,  B81C2201/0181

Abstract: An example provides a method including sputtering a metal catalyst onto a substrate, exposing the substrate to a solution that reacts with the metal catalyst to form a plurality of pores in the substrate, and etching the substrate to remove the plurality of pores to form a recess in the substrate.

公开(公告)号：US09511998B2

公开(公告)日：2016-12-06

申请号：US14207752

申请日：2014-03-13

Applicant: Robert Bosch GmbH

Inventor： Ashwin Samarao ,  Gary O'Brien ,  Ando Feyh ,  Gary Yama ,  Andrew Graham ,  Bongsang Kim ,  Fabian Purkl

IPC: H01L21/322 ,  B81C1/00 ,  H01L23/28

CPC classification number: B81C1/00285 ,  B81C2201/0115 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/3223 ,  H01L21/3225 ,  H01L23/28

Abstract: A microelectromechanical system (MEMS) device includes a high density getter. The high density getter includes a silicon surface area formed by porosification or by the formation of trenches within a sealed cavity of the device. The silicon surface area includes a deposition of titanium or other gettering material to reduce the amount of gas present in the sealed chamber such that a low pressure chamber is formed. The high density getter is used in bolometers and gyroscopes but is not limited to those devices.

Abstract translation: 微机电系统（MEMS）装置包括高密度吸气剂。 高密度吸气剂包括通过孔化形成的硅表面积或通过在该装置的密封腔内形成沟槽。 硅表面积包括钛或其它吸气材料的沉积物，以减少密封室中存在的气体的量，从而形成低压室。 高密度吸气剂用于测辐射仪和陀螺仪，但不限于这些设备。

公开(公告)号：US20160244885A1

公开(公告)日：2016-08-25

申请号：US15033015

申请日：2013-10-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Roger A. McKay ,  Patrick W. Sadik

IPC: C23F1/16

CPC classification number: B81C1/00539 ,  B81B2201/058 ,  B81C1/00119 ,  B81C2201/0115 ,  B81C2201/014 ,  C23C14/5873 ,  C23F1/02 ,  C23F1/16 ,  H01M4/0492 ,  H01M4/386

Abstract: Etching islands are formed on a first face of a substrate and a second face of the substrate non-parallel to the first face. The first face and the second face of the substrate are concurrently exposed to a solution that reacts with the etching islands to concurrently form porous regions extending into the first face and the second face.

Abstract translation: 在基板的第一面和不平行于第一面的基板的第二面上形成蚀刻岛。 衬底的第一面和第二面同时暴露于与蚀刻岛反应的溶液，以同时形成延伸到第一面和第二面的多孔区域。

公开(公告)号：US09272899B2

公开(公告)日：2016-03-01

申请号：US14591896

申请日：2015-01-07

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Rama Krishna Kotlanka ,  Rakesh Kumar ,  Premachandran Chirayarikathuveedu Sankarapillai ,  Huamao Lin ,  Pradeep Yelehanka

IPC: H01L23/48 ,  H01L25/065 ,  B81B7/00 ,  H01L21/50 ,  B81C1/00 ,  B81C3/00 ,  H01L23/522

CPC classification number: B81B7/0006 ,  B81C1/00269 ,  B81C3/001 ,  B81C2201/0115 ,  H01L21/50 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

公开(公告)号：US20140069185A1

公开(公告)日：2014-03-13

申请号：US13607352

申请日：2012-09-07

Applicant: Xiang Zheng Tu

Inventor： Xiang Zheng Tu

IPC: G01F1/688 ,  H01L35/34 ,  G01F1/692

CPC classification number: G01F1/692 ,  B81C1/00158 ,  B81C1/00246 ,  B81C1/00571 ,  B81C2201/0115 ,  B81C2201/0142 ,  G01F1/6845 ,  G01F1/688 ,  H01L21/3063 ,  H01L35/34

Abstract: A vacuum-cavity-insulated flow sensor and related fabrication method are described. The sensor comprises a porous silicon wall with numerous vacuum-pores which is created in a silicon substrate, a porous silicon membrane with numerous vacuum-pores which is surrounded and supported by the porous silicon wall, and a cavity with a vacuum-space which is disposed beneath the porous silicon membrane and surrounded by the porous silicon wall. The fabrication method includes porous silicon formation and silicon polishing in HF solution.

Abstract translation: 描述了真空腔绝缘流量传感器及相关的制造方法。 传感器包括具有许多真空孔的多孔硅壁，其形成于硅衬底中，多孔硅膜具有许多真空孔，该多孔硅膜被多孔硅壁包围和支撑，以及具有真空空间的空腔， 设置在多孔硅膜下方并被多孔硅壁包围。 制造方法包括HF溶液中的多孔硅形成和硅研磨。

公开(公告)号：US20140030847A1

公开(公告)日：2014-01-30

申请号：US13559626

申请日：2012-07-27

Applicant: Rama Krishna KOTLANKA ,  Rakesh KUMAR ,  Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI ,  Huamao LIN ,  Pradeep YELEHANKA

Inventor： Rama Krishna KOTLANKA ,  Rakesh KUMAR ,  Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI ,  Huamao LIN ,  Pradeep YELEHANKA

IPC: H01L21/762

CPC classification number: B81B7/0006 ,  B81C1/00269 ,  B81C3/001 ,  B81C2201/0115 ,  H01L21/50 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Abstract translation: 公开了具有至少一个孔隙化表面的粘合装置。 孔化过程将纳米多孔孔引入装置的结合表面的微结构中。 与非孔隙化材料相比，孔化材料的材料性质更软。 对于相同的接合条件，与非孔隙化材料相比，使用孔隙化粘合表面增强了粘结界面的粘结强度。

公开(公告)号：US08217476B2

公开(公告)日：2012-07-10

申请号：US12817937

申请日：2010-06-17

Applicant: Karl-Heinz Kraft ,  Simon Armbruster ,  Arnim Hoechst

Inventor： Karl-Heinz Kraft ,  Simon Armbruster ,  Arnim Hoechst

IPC: H01L21/00

CPC classification number: B81C1/00158 ,  B81C2201/0115 ,  B81C2201/0191

Abstract: A method for manufacturing a micromechanical component and the micromechanical component produced thereby. This component is preferably a diaphragm or a diaphragm layer which is independently produced for the purpose of subsequent assembly with other components.

Abstract translation: 一种制造微机械部件的方法和由此制造的微机械部件。 该部件优选是隔膜或隔膜层，其独立地用于随后与其它部件组装的目的。

公开(公告)号：US08123963B2

公开(公告)日：2012-02-28

申请号：US12152241

申请日：2008-05-12

Applicant: Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

IPC: H01L21/302 ,  B81C1/00

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C1/00595 ,  B81C2201/0115 ,  G01L9/0045 ,  H01L21/3063

Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.

Abstract translation: 一种制造半导体部件的方法包括在所述半导体部件的p掺杂层中形成n掺杂层，其中所述n掺杂层包括以下中的至少一种：筛状层或网状层。 该方法还包括在n掺杂层的材料之间对p-掺杂层进行腐蚀蚀刻以形成顶部电极，以及在n-掺杂层下方形成空腔。