中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

475 records (took 0.031 seconds)

    Executing permutations
    132.
    发明公开
    Executing permutations 有权
    Ausführungvon Permutationen

    公开(公告)号：EP0932273A1

    公开(公告)日：1999-07-28

    申请号：EP99300100.7

    申请日：1999-01-06

    Applicant: STMicroelectronics Limited

    Inventor： Cole, Anthony James

    IPC: H04L9/06 ,  H04L9/34

    CPC classification number: H04L9/0625 ,  H04L2209/046 ,  H04L2209/12

    Abstract: A method for changing the bit-order of a data value in a data processing system having a register capable of storing data strings which each comprise a plurality of sub-strings that are not individually addressable, the method comprising assigning an output data string by the steps of: loading the data value into a first data string; generating, for each sub-string of the output data string, a corresponding intermediate data string, each sub-string of which corresponds to a selected bit on the first data string and has all its bits equal to the value of the selected bit; and
    and generating the output data string, in each sub-string of which each bit has the same value as the bits in a selected sub-string of the intermediate data string that corresponds to that sub-string of the output data string.

    Abstract translation: 一种用于改变数据处理系统中的数据值的位顺序的方法，该数据处理系统具有能够存储数据串的寄存器，每个数据串包括不能单独寻址的多个子串，该方法包括：通过 步骤：将数据值加载到第一数据串中; 为输出数据串的每个子串生成对应的中间数据串，其每个子串对应于第一数据串上的所选位，并且其所有位等于所选位的值; 并且在每个子串的每个子串中产生与输出数据串的该子串相对应的中间数据串的所选子串中的位相同的值的每个子串中的输出数据串。

    Run-length encoding
    134.
    发明公开
    Run-length encoding 有权
    Lauflängenkodierung

    公开(公告)号：EP0928100A1

    公开(公告)日：1999-07-07

    申请号：EP98310007.4

    申请日：1998-12-07

    Applicant: STMicroelectronics Limited

    Inventor： Watson, Victor Robert

    IPC: H04N1/415 ,  H04N1/419 ,  H04N7/32 ,  H03M7/46

    CPC classification number: H03M7/40 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  H03M7/46 ,  H04N1/415 ,  H04N1/419 ,  H04N19/42 ,  H04N19/61 ,  H04N19/93

    Abstract: A method for run-length encoding two or more data values, the method comprising: loading the data values into storage by forming a first data string, the data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values; generating a second data string having a data sub-string corresponding to each data sub-string of the first data string, all the bits of each of the data sub-strings of the second data string having a first predetermined value if all the bits of the corresponding data sub-string of the first data string have a second predetermined value and having a third predetermined value if any of the bits of the corresponding data sub-string of the first data string has other than the second predetermined value; starting from a predetermined end of the second data string, counting the number of consecutive bits of the second data spring having the first predetermined value; and dividing the said number by the number of bits in each data sub-string.

    Abstract translation: 一种用于游程长度编码两个或多个数据值的方法，所述方法包括：通过形成第一数据串将数据值加载到存储器中，所述数据串包括多个数据子串，并且每个数据子串至少表示 数据值之一; 生成具有对应于第一数据串的每个数据子串的数据子串的第二数据串，如果所有位都是第二数据串的每个数据子串的所有位都具有第一预定值 如果第一数据串的对应数据子串中的任何一个位都不具有第二预定值，则第一数据串的相应数据子串具有第二预定值并具有第三预定值; 从第二数据串的预定端开始，对具有第一预定值的第二数据弹簧的连续位数进行计数; 并将所述数除以每个数据子串中的位数。

    Method and computer system for processing a data stream
    135.
    发明公开
    Method and computer system for processing a data stream 审中-公开
    Verfahren und Rechnersystem zur Verarbeitung eines Datenstroms

    公开(公告)号：EP0927937A1

    公开(公告)日：1999-07-07

    申请号：EP98310189.0

    申请日：1998-12-11

    Applicant: STMicroelectronics Limited

    Inventor： McIntosh-Smith, Simon

    IPC: G06F12/08

    CPC classification number: G06F12/0848 ,  G06F12/0842 ,  Y10T74/1519 ,  Y10T74/1531

    Abstract: A method and computer for processing an incoming data stream, for example of video or audio data is described. A system memory is divided into first and second memory spaces, the first memory space for holding a data stream and the second memory space for holding a set of program data. A cache has first and second partitions allocated exclusively respectively to the first and second memory spaces. In this manner, when the data stream is transferred between an execution unit and the main memory, program data is not evicted from the cache.

    Abstract translation: 描述了用于处理输入数据流（例如视频或音频数据）的方法和计算机。 系统存储器分为第一和第二存储器空间，用于保存数据流的第一存储器空间和用于保存一组程序数据的第二存储器空间。 高速缓存具有分配给第一和第二存储器空间的第一和第二分区。 以这种方式，当数据流在执行单元和主存储器之间传送时，程序数据不会从高速缓存中逐出。

    A programmable divider circuit
    136.
    发明公开
    A programmable divider circuit 有权
    Programmierbare Teilerschaltung

    公开(公告)号：EP0926834A1

    公开(公告)日：1999-06-30

    申请号：EP98310160.1

    申请日：1998-12-11

    Applicant: STMicroelectronics Limited

    Inventor： Monk, Trevor

    IPC: H03K23/66 ,  H03K23/54

    CPC classification number: H03L7/183 ,  H03K23/544 ,  H03K23/66 ,  H03K23/667

    Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages (B1,B2) connected in a divide-by-N sequence, where N is an odd integer, the transistor stages being configured so that when the output of the last stage is supplied to the first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages, a tri-state inverter (T) selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages (B1,B3,B4), where M is an even integer, and wherein the second plurality includes at least some of said first plurality of transistor stages, including said first stage, whereby when the output of the last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages, and a switching circuit (MUX) having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

    Abstract translation: 可编程分频电路包括以N分频序列连接的第一多个N个相似的晶体管级（B1，B2），其中N为奇整数，晶体管级被配置为使得当最后级的输出为 按照序列提供给第一级，分频电路作为N分频电路工作，其中产生输出信号，对于施加到晶体管级的时钟信号的每N个周期，具有一个周期，三态 逆变器（T）可以以M分频序列与第二多个M个晶体管级（B1，B3，B4）连接，其中M是偶数整数，并且其中第二多个包括所述第一多个 包括所述第一级，由此当M分频序列中的最后级的输出被提供给第一级时，该电路作为产生输出信号的除M电路工作 对于a的每个M个周期，其具有一个周期 施加到晶体管级的时钟信号，以及具有至少两个输入的开关电路（MUX），并且被布置为以N分频或分频方式选择性地将最后级的输出连接到第一级， M序列，由此电路可以被编程为以N分频或M分频电路工作。

    A dividing circuit and transistor stage therefor
    137.
    发明公开
    A dividing circuit and transistor stage therefor 审中-公开
    Teilerschaltung und Transistorstufedafür

    公开(公告)号：EP0926833A1

    公开(公告)日：1999-06-30

    申请号：EP98310190.8

    申请日：1998-12-11

    Applicant: STMicroelectronics Limited

    Inventor： Monk, Trevor

    IPC: H03K23/54 ,  H03K23/44 ,  H03K23/66 ,  H03L7/183

    CPC classification number: H03L7/183 ,  H03K23/44 ,  H03K23/544 ,  H03K23/66

    Abstract: A dividing circuit comprises a plurality (N) of transistor stages connected in a ring. Each stage comprises a first pair of transistors of a first conductivity type (T1,T2) connected in series between a first voltage level (Vdd) and an output node (O1), a second pair of transistors of a second conductivity type (T3,T4) connected in series between a second voltage level and said output node (O1),
       wherein control nodes of a first transistor (T1,T4) of each said transistor pair are connected together to provide an input node (I1) for the stage, and control nodes of a second transistor (T2,T3) of each said transistor pair are connected together to provide a clock node (CLK IN) for the stage, wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than the duty cycle of said clock signal.

    Abstract translation: 分频电路包括以环形连接的多个（N）个晶体管级。 每个级包括串联连接在第一电压电平（Vdd）和输出节点（O1）之间的第一导电类型（T1，T2）的第一对晶体管，第二导电类型的第二对晶体管（T3， T4）串联连接在第二电压电平和所述输出节点（O1）之间，其中每个所述晶体管对的第一晶体管（T1，T4）的控制节点连接在一起以提供用于该级的输入节点（I1） 并且每个所述晶体管对的第二晶体管（T2，T3）的控制节点连接在一起以为所述级提供时钟节点（CLK IN），其中每一级的输入节点连接到前一级的输出节点 由此在每个所述输出节点处产生输出信号，每个周期的输出信号表示施加到级的所述时钟节点的时钟信号的N个周期，输出信号的占空比接近50％ 所述时钟信号的占空比。

Patent Agency Ranking