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公开(公告)号：KR1020040021260A
公开(公告)日：2004-03-10
申请号：KR1020020052857
申请日：2002-09-03
Applicant: 삼성전자주식회사
IPC: G02F1/136
CPC classification number: G02F1/136 , G02F2001/136295 , G02F2201/123 , H01L29/786
Abstract: PURPOSE: A thin film transistor substrate using a low-resistance line and a liquid crystal display including the thin film transistor substrate are provided to remove a parasitic resistance to obtain a high aperture ratio. CONSTITUTION: A liquid crystal display includes a thin film transistor substrate. The thin film transistor substrate includes data lines. The data lines contain Co, Ni or an alloy of Co and Ni. The data lines include a gate structure(26) that is formed of a Co single film, a Ni single film, a Co/AlNd layer, or a Ni/AlNd layer. The data lines include a source/drain structure(65,66) that is formed of a Co single film, a Ni single film, a Ci/AlNd/Co layer, or a Ni/AlNd/Ni layer.
Abstract translation: 目的：提供使用低电阻线的薄膜晶体管基板和包括薄膜晶体管基板的液晶显示器，以消除寄生电阻以获得高开口率。 构成：液晶显示器包括薄膜晶体管基板。 薄膜晶体管基板包括数据线。 数据线包含Co，Ni或Co和Ni的合金。 数据线包括由Co单膜，Ni单膜，Co / AlNd层或Ni / AlNd层形成的栅极结构（26）。 数据线包括由Co单膜，Ni单膜，Ci / AlNd / Co层或Ni / AlNd / Ni层形成的源极/漏极结构（65,66）。
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公开(公告)号：KR1020030095605A
公开(公告)日：2003-12-24
申请号：KR1020020032884
申请日：2002-06-12
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L21/28008 , G03F7/0047 , H01L21/288 , H01L21/32051 , H01L27/12 , H01L27/124 , H01L29/66765 , H01L29/78669 , H01L51/0003 , H01L51/0015 , H01L51/0021 , H01L51/0545
Abstract: PURPOSE: A method for forming a metal pattern and a method for manufacturing a TFT(Thin Film Transistor) substrate using the same are provided to be capable of simplifying manufacturing processes by exposing and developing a photosensitive organic metal layer for forming the metal pattern. CONSTITUTION: An organic metal layer is formed by coating photosensitive organic metal adhering agent. An exposure process is carried out at the organic metal layer by using a photo mask. A metal pattern is formed by carrying out a development process at the organic metal layer. Preferably, the organic metal layer developing process is carried out by using organic solution. Preferably, a light blocking pattern of the photo mask is formed into a predetermined shape.
Abstract translation: 目的：提供一种用于形成金属图案的方法和使用其的制造TFT（薄膜晶体管）基板的方法，以便通过曝光和显影用于形成金属图案的光敏有机金属层来简化制造工艺。 构成：通过涂布感光性有机金属粘合剂形成有机金属层。 通过使用光掩模在有机金属层进行曝光处理。 通过在有机金属层进行显影处理来形成金属图案。 优选地，有机金属层显影处理通过使用有机溶液进行。 优选地，光掩模的遮光图案形成为预定的形状。
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公开(公告)号：KR1020030058862A
公开(公告)日：2003-07-07
申请号：KR1020020000097
申请日：2002-01-02
Applicant: 삼성전자주식회사
IPC: G02F1/136
CPC classification number: G02F1/136227 , G02F1/136213 , G02F2001/13629
Abstract: PURPOSE: A line structure, a thin film transistor substrate using the same, and a method for manufacturing thereof are provided to realize low resistance line, and complement bonding power and chemical-resistance of Ag. CONSTITUTION: A plurality of gate wires(22,24,26) are formed on an insulating substrate(10). A first insulating film(30) is formed on the gate wires. A plurality of data wires(65,66,68) are formed on the first insulating film and cross the gate wires. Thin film transistors are electrically connected with the gate wires and the data wires. A passivation film(70) is formed on the thin film transistors and has first contact holes(76) exposing drain electrodes of the thin film transistors. A pixel electrode(82) is formed on the passivation film and is connected with the drain electrodes through the contact holes. The gate wires and the data wires are triple layers made up of bonding layers, Ag layer, and passivation layers. The bonding layer is formed of anyone of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta, and Ta alloy. The Ag layer is formed of Ag or Ag alloy. The passivation layer is formed of anyone of IZO, Mo, Mo alloy, Cr, and Cr alloy.
Abstract translation: 目的：提供线结构，使用其的薄膜晶体管基板及其制造方法，以实现低电阻线，并且补充Ag的结合力和耐化学性。 构成：在绝缘基板（10）上形成多个栅极线（22,24,26）。 在栅极线上形成第一绝缘膜（30）。 多个数据线（65,66,68）形成在第一绝缘膜上并与栅极线交叉。 薄膜晶体管与栅极线和数据线电连接。 钝化膜（70）形成在薄膜晶体管上，并且具有暴露薄膜晶体管的漏电极的第一接触孔（76）。 像素电极（82）形成在钝化膜上并通过接触孔与漏电极连接。 栅极线和数据线是由结合层，Ag层和钝化层构成的三层。 接合层由Cr，Cr合金，Ti，Ti合金，Mo，Mo合金，Ta和Ta合金中的任何一种形成。 Ag层由Ag或Ag合金形成。 钝化层由IZO，Mo，Mo合金，Cr和Cr合金中的任何一种形成。
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公开(公告)号：KR1020030016051A
公开(公告)日：2003-02-26
申请号：KR1020010049963
申请日：2001-08-20
Applicant: 삼성전자주식회사
IPC: G02F1/136
CPC classification number: G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629
Abstract: PURPOSE: A thin film transistor substrate for a liquid crystal display and a method for manufacturing the same are provided to design uniform process conditions and minimize contact resistance at contact parts by forming a low resistance conductive layer, thereby improving the reliability of the contact parts. CONSTITUTION: A method for manufacturing a thin film transistor substrate for a liquid crystal display includes the steps of forming gate wires including gate lines(22) and gate electrodes(26) connected with the gate lines by using a conductive film for gate wires on an insulating substrate; forming a gate insulating film; forming a semiconductor layer(40) on the gate insulating film; forming data wires including data lines(62) crossing the gate lines, source electrodes(65) connected with the data lines and adjacent to the gate electrodes, and drain electrodes(66) opposite to the source electrodes related to the gate electrodes; forming first contact holes(76,78) exposing the drain electrodes by accumulating and patterning a protective layer; forming pixel electrodes(82) electrically connected with the exposed drain electrodes; and forming low resistance conductive films(200,600) including a conductive material for the gate wires or the data wires, and nitrogen on the gate wires or the data wires.
Abstract translation: 目的：提供一种用于液晶显示器的薄膜晶体管基板及其制造方法，以通过形成低电阻导电层来设计均匀的工艺条件并使接触部分的接触电阻最小化，从而提高接触部件的可靠性。 构成：用于制造液晶显示器用薄膜晶体管基板的方法包括以下步骤：通过使用栅极线上的导电膜形成栅极线，该栅极线包括栅极线（22）和与栅极线连接的栅电极（26） 绝缘基板; 形成栅极绝缘膜; 在栅极绝缘膜上形成半导体层（40）; 形成数据线，包括与栅极线交叉的数据线（62），与数据线连接并与栅电极相邻的源电极（65）以及与栅电极相关的源电极相对的漏电极（66） 形成通过累积和图案化保护层来暴露所述漏电极的第一接触孔（76,78） 形成与所述暴露的漏电极电连接的像素电极（82） 以及形成包括用于栅极线或数据线的导电材料的低电阻导电膜（200,600），以及栅极线或数据线上的氮。
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公开(公告)号：KR1020020032212A
公开(公告)日：2002-05-03
申请号：KR1020000063245
申请日：2000-10-26
Applicant: 삼성전자주식회사
IPC: G02F1/136
Abstract: PURPOSE: A thin film transistor substrate for a liquid crystal display and a method of fabricating the substrate are provided to form a conducting line having excellent corrosion-resistance and low resistance. CONSTITUTION: A thin film transistor substrate for a liquid crystal display includes an insulating substrate(10), a gate line(21,22,23) having a gate electrode formed on the substrate, a gate insulating layer(30) formed on the gate lines, and a semiconductor layer(41) formed on the gate insulating layer. The substrate further includes a data line(61,62,63,64) that is formed on the semiconductor layer and has source and drain electrodes, a passivation layer(70) having the first contact hole(72) exposing the drain electrode, and a pixel electrode(80) connected to the drain electrode through the first contact hole. At least one of the gate line and data line is made of a silver alloy layer and an IZO layer. The IZO layer is formed on the silver alloy layer and covers the side of the silver alloy layer.
Abstract translation: 目的：提供用于液晶显示器的薄膜晶体管基板和制造基板的方法，以形成具有优异的耐腐蚀性和低电阻的导线。 构成：用于液晶显示器的薄膜晶体管衬底包括绝缘衬底（10），在衬底上形成有栅电极的栅极线（21,22,23），形成在栅极上的栅极绝缘层（30） 线，以及形成在栅极绝缘层上的半导体层（41）。 衬底还包括形成在半导体层上并具有源极和漏极的数据线（61,62,63,64），具有暴露漏电极的第一接触孔（72）的钝化层（70），以及 通过第一接触孔与漏电极连接的像素电极（80）。 栅极线和数据线中的至少一个由银合金层和IZO层制成。 IZO层形成在银合金层上并覆盖银合金层的一侧。
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Patent Agency Ranking
公开(公告)号：KR1020010097215A
公开(公告)日：2001-11-08
申请号：KR1020000021083
申请日：2000-04-20
Applicant: 삼성전자주식회사
IPC: G02F1/136
Abstract: 절연 기판 위에 게이트선과 게이트 전극 및 게이트 패드를 포함하는 게이트 배선을 형성하고, 그 위에 게이트 절연막, 반도체층 및 저항성 접촉층을 형성한다. 저항성 접촉층 및 게이트 절연막 위에 크롬, 티타늄 또는 몰리브덴 중 어느 하나를 포함하는 하부막과 알루미늄 합금막을 포함하는 상부막으로 이루어진 이중막으로 데이터선과 소스 전극, 드레인 전극 및 데이터 패드를 포함하는 데이터 배선을 형성한다. 그 위에 보호막을 증착하고 드레인 전극, 게이트 패드 및 데이터 패드를 드러내는 접촉 구멍을 형성한다. 보호막 위에 IZO와 같은 투명 도전 물질을 증착하고 패터닝하여 화소 전극, 보조 게이트 패드 및 보조 데이터 패드를 형성한다. 여기서, 게이트 배선과 데이터 배선의 상부막을 알루미늄 합금막으로 형성하되, 첨가 성분이 Ti, Ta, Zr 및 Cu와 같은 전이 금속 또는 Nd 및 Y와 같은 희토류 금속 중 하나 이상을 포함하도록 하고 그 함량을 1at% 내지 10at%, 더욱 바람직하게는 1at% 내지 6at%으로 하여 IZO 막과의 접촉 저항을 줄이며 제조 공정을 단순화한다.
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公开(公告)号：KR1020010010117A
公开(公告)日：2001-02-05
申请号：KR1019990028823
申请日：1999-07-16
Applicant: 삼성전자주식회사
IPC: G02F1/136
Abstract: PURPOSE: A method of making a thin film transistor substrate is provided to prevent a cavity made around a drain electrode by forming a photoresist film pattern or an organic insulating film pattern the thickness of which is partially different. CONSTITUTION: The method of making a thin film transistor substrate comprises sequentially forming a gate insulating film(30), a semiconductor layer(40) and a data metal layer on a gate wire. A data wire, which is comprised of source and drain electrodes(65,66,75,76) and data pads(64,74), is formed by patterning the data metal layer. A passivation film(80) is formed on the data wire. A gate insulating film pattern having the first contact hole for exposing the gate pads(14,24) is formed by patterning the semiconductor layer(40) and the gate insulating film(30) together with the passivation film. A semiconductor layer pattern is formed which has the first opening for exposing the gate insulating film between the data wires. A passivation film pattern is formed which has the second contact hole for exposing the data pads(64,74) and the second opening for exposing the gate insulating film, exposed through the first opening, with the drain electrode. A pixel electrode is formed on the gate insulating film so as to be connected to the drain electrode.
Abstract translation: 目的：提供制造薄膜晶体管基板的方法，以通过形成其厚度部分不同的光致抗蚀剂图案或有机绝缘膜图案来防止在漏电极周围形成的空腔。 构成：制造薄膜晶体管衬底的方法包括在栅极线上顺序地形成栅极绝缘膜（30），半导体层（40）和数据金属层。 通过对数据金属层进行构图而形成由源极和漏极（65,66,75,76）和数据焊盘（64,74）组成的数据线。 在数据线上形成钝化膜（80）。 通过使半导体层（40）和栅极绝缘膜（30）与钝化膜一起构图，形成具有用于暴露栅极焊盘（14,24）的第一接触孔的栅极绝缘膜图案。 形成半导体层图案，其具有用于在数据线之间暴露栅极绝缘膜的第一开口。 形成钝化膜图案，其具有用于暴露数据焊盘（64,74）的第二接触孔和用于将通过第一开口暴露的栅极绝缘膜暴露于漏电极的第二开口。 在栅极绝缘膜上形成像素电极，以连接到漏电极。
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138.发明公开
公开(公告)号：KR1020000073181A
公开(公告)日：2000-12-05
申请号：KR1019990016315
申请日：1999-05-07
Applicant: 삼성전자주식회사
Inventor： 정창오
IPC: H01L29/786
Abstract: PURPOSE: A method for manufacturing a substrate of a TFT(Thin Film Transistor) for a LCD(Liquid Crystal Display) is provided to simplify a manufacturing process, by patterning a layer without an etch process, and by using the layer to pattern as an etch blocking layer for patterning a lower layer of the layer to pattern. CONSTITUTION: A gate interconnection including a gate line/a gate electrode of a screen display area and a gate pad of a peripheral area, is formed on a substrate including the screen display area and the peripheral area. A gate insulating layer, a semiconductor layer, a contact layer and a conductive layer are consecutively evaporated on the gate interconnection. A data interconnection and a contact layer pattern under the data interconnection including a data line, a source/drain electrode and a data pad are formed by etching the conductive layer and contact layer. A passivation layer composed of a photo-resistive organic insulating material is stacked. The passivation layer is exposed by using a first and a second optical masks having different light transmission rates. The passivation layer is developed to form another passivation layer having a different thickness. A passivation layer pattern and a semiconductor layer pattern are formed by patterning the passivation layer and semiconductor layer under the passivation layer of the screen display area while the passivation layer, semiconductor layer and gate insulating layer of the peripheral area are patterned to form a first contact window exposing the gate pad. A pixel electrode is electrically connected to a drain electrode.
Abstract translation: 目的：提供一种用于制造用于LCD（液晶显示器）的TFT（薄膜晶体管）的基板的方法，用于通过在没有蚀刻工艺的情况下对图案进行图案化，并且通过使用该层将其图案化为简化制造工艺 蚀刻阻挡层，用于图案化该层的下层以进行图案化。 构成：包括屏幕显示区域的栅极线/栅电极和周边区域的栅极焊盘的栅极互连形成在包括屏幕显示区域和周边区域的基板上。 栅极绝缘层，半导体层，接触层和导电层在栅极互连上连续蒸发。 通过蚀刻导电层和接触层来形成包括数据线，源极/漏极和数据焊盘在内的数据互连下的数据互连和接触层图案。 层叠由光电性有机绝缘材料构成的钝化层。 钝化层通过使用具有不同透光率的第一和第二光掩模曝光。 显影钝化层以形成具有不同厚度的另一钝化层。 通过在屏幕显示区域的钝化层下方的钝化层和半导体层图案化而形成钝化层图案和半导体层图案，同时对外围区域的钝化层，半导体层和栅极绝缘层进行图案化以形成第一接触 窗户露出门板。 像素电极电连接到漏电极。
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公开(公告)号：KR100176175B1
公开(公告)日：1999-03-20
申请号：KR1019950051050
申请日：1995-12-16
Applicant: 삼성전자주식회사
IPC: H01L29/786
Abstract: 신규한 박막트랜지스터-액정표시소자의 제조방법이 개시되어 있다. 탭 집적회로가 본딩되는 패드 부위까지 알루미늄 합금으로 이루어진 게이트를 형성한다. 결과물 상에 액티브 패턴, 소옷/드레인 및 화소패턴을 차례로 형성한다. 결과물 상에 패시베이션층을 형성한 후, 이를 식각하여 게이트 패드, 소오스/드레인 패드 및 화소패턴 부위를 동시에 개구시킨다. 소오스/드레인 형성전의 HF 세정공정 및 화소 ITO 증착공정시 알루미늄 합금이 노출되지 않는다.
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公开(公告)号：KR1019980051666A
公开(公告)日：1998-09-25
申请号：KR1019960070577
申请日：1996-12-23
Applicant: 삼성전자주식회사
Inventor： 정창오
IPC: G02F1/1343 , G02F1/136
Abstract: 본 발명은 액정 표시 장치에 관한 것으로서, 마이그레이션 레지스턴트 알루미늄 합금을 게이트 배선으로 사용한 액정 표시 장치에 관한 것이다.
박막 트랜지스터 기판의 게이트 전극 및 게이트 라인 등의 게이트 배선 물질로 Al-Nd, Al-Ti 등의 2원소 Al 합금에 마이그레이션을 방지할 Cu 또는 Pd 등의 제3원소를 참가한 합금을 사용한 것이 특징이다.
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