公开(公告)号：KR1020050077457A

公开(公告)日：2005-08-02

申请号：KR1020040005520

申请日：2004-01-28

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  김재학 ,  위영진 ,  이승진 ,  박기관

IPC: H01L21/28

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76829

Abstract: 반도체 소자의 배선 방법 및 배선 구조체를 제공한다. 상기 반도체 소자의 배선방법은 반도체기판 상에 층간절연막을 형성하는 것을 구비하되, 상기 층간절연막은 탄소 도핑된 저유전율막으로 형성한다. 상기 층간절연막 상에 산화방지막을 형성한다. 상기 산화방지막 상에 산화물 캐핑층을 형성한다. 상기 산화물 캐핑층, 상기 산화방지막 및 상기 층간절연막을 관통하는 비아홀을 형성한다. 상기 비아홀 내에 도전막 패턴을 형성한다.

公开(公告)号：KR100391992B1

公开(公告)日：2003-07-22

申请号：KR1020010036933

申请日：2001-06-27

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  신홍재 ,  이수근 ,  이경우

IPC: H01L21/283

Abstract: PURPOSE: A method for forming a semiconductor device having low permittivity interlayer dielectric is provided to exactly form a micro pattern on a SiOC layer and to restrain a parasitic capacitance between interconnections or contact plugs by using the SiOC layer having a low dielectric constant. CONSTITUTION: A low permittivity carbon oxide silicon layer made of SiOC is formed on a substrate(100) by a CVD(Chemical Vapour Deposition) using a nitrogen included gas as a source gas or a carrier gas. A plasma processing is performed on the carbon oxide silicon layer by supplying gases, such as a helium, a hydrogen, an N2O, or an Ar gas to a processing chamber. A photoresist is deposited and patterned on the plasma processed carbon oxide silicon layer(111).

Abstract translation: 目的：提供一种形成具有低介电常数层间电介质的半导体器件的方法，以在SiOC层上精确地形成微图案，并通过使用具有低介电常数的SiOC层来抑制互连或接触插塞之间的寄生电容。 构成：使用含氮气体作为源气体或载气，通过CVD（化学气相沉积）在衬底（100）上形成由SiOC制成的低介电常数碳氧化硅层。 通过向处理室供给诸如氦气，氢气，N 2 O或Ar气体的气体在碳氧化硅层上执行等离子体处理。 在等离子体处理的碳氧化硅层（111）上沉积并构图光致抗蚀剂。

公开(公告)号：KR100365641B1

公开(公告)日：2002-12-26

申请号：KR1020000043961

申请日：2000-07-29

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  신홍재 ,  한재현

IPC: H01L21/28

Abstract: 본 발명은 배선의 기생 용량을 줄일 수 있는 반도체 장치 및 그 형성방법에 관한 것으로, 그 형성방법은 기판에 무기 실리콘 산화막과 저유전율 유기 실리콘 산화막을 차례로 적층하는 단계, 패터닝 과정을 통해 상기 유기 실리콘 산화막에 상기 유기 실리콘 산화막 두께의 일부를 깊이로 하는 부분 트렌치를 형성하는 단계, 상기 부분 트렌치 내벽면에 대한 산소 처리를 하는 단계, 상기 부분 트렌치에 대한 불산 습식 식각을 실시하여 트렌치를 완성하는 단계를 구비하여 이루어진다.

公开(公告)号：KR1020020085072A

公开(公告)日：2002-11-16

申请号：KR1020010024339

申请日：2001-05-04

Applicant: 삼성전자주식회사

Inventor： 신홍재 ,  김재학 ,  이수근 ,  이경우

IPC: H01L21/28

Abstract: PURPOSE: A gate spacer structure and a method for forming the same are provided to prevent bridge between a gate pattern and a bit line by entirely covering a gate electrode using silicon nitride as a spacer. CONSTITUTION: A gate pattern(200) sequentially stacked on a gate oxide pattern(110), a gate electrode(120) and a capping insulator pattern(130) is formed on a semiconductor substrate(100). An oxide spacer(141) is formed at both sidewalls of the gate electrode(120) and the gate oxide pattern(110). Also, a gate spacer(161) is formed at both sidewalls of the oxide spacer(141) and the capping insulator pattern(130). Thereby, the capping insulator pattern(130) is directly connected to the gate spacer(161). Therefore, the gate electrode(120) and the gate oxide pattern(110) are entirely covered by the capping insulator pattern(130) and the gate spacer(161). The capping insulator pattern(130) and the gate spacer(161) are made of silicon nitride.

Abstract translation: 目的：提供一种栅极间隔结构及其形成方法，以通过使用氮化硅作为间隔物来完全覆盖栅电极来防止栅极图案和位线之间的桥接。 构成：在半导体衬底（100）上形成顺序堆叠在栅极氧化物图案（110）上的栅极图案（200），栅电极（120）和封盖绝缘体图案（130）。 在栅极（120）和栅极氧化物图案（110）的两个侧壁处形成氧化物间隔物（141）。 此外，在氧化物间隔物（141）和封盖绝缘体图案（130）的两个侧壁处形成栅极间隔物（161）。 由此，封盖绝缘体图案130直接连接到栅极间隔物161。 因此，栅极电极（120）和栅极氧化物图案（110）完全被封盖绝缘体图案（130）和栅极间隔物（161）覆盖。 封盖绝缘体图案（130）和栅极间隔物（161）由氮化硅制成。

公开(公告)号：KR1020020084735A

公开(公告)日：2002-11-11

申请号：KR1020010023751

申请日：2001-05-02

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  이수근

IPC: H01L21/3065

Abstract: PURPOSE: A method and an apparatus for removing a photoresist formed on an interlayer dielectric of a semiconductor device are provided to maintain a dielectric constant of the interlayer dielectric after an ashing process is performed on the photoresist formed on the interlayer dielectric. CONSTITUTION: An interlayer dielectric of a low dielectric constant is formed on a surface of a semiconductor substrate(S1). A photoresist is coated on an upper portion of the interlayer dielectric(S2). A contact hole is formed by patterning the photoresist and the interlayer dielectric(S3). The photoresist is removed by performing an ashing process for the photoresist and the interlayer dielectric is exposed thereby(S4). The interlayer dielectric is contacted with activated hydrogen by performing an activated hydrogen process(S5). A post-process such as a stripping process is performed(S6). The interlayer dielectric is formed by an SiOC:H-based compound. The activated hydrogen includes hydrogen plasma.

Abstract translation: 目的：提供一种用于去除形成在半导体器件的层间电介质上的光致抗蚀剂的方法和装置，以在对形成在层间电介质上的光致抗蚀剂进行灰化处理之后维持层间电介质的介电常数。 构成：在半导体衬底的表面上形成低介电常数的层间电介质（S1）。 光致抗蚀剂涂覆在层间电介质的上部（S2）上。 通过图案化光致抗蚀剂和层间电介质形成接触孔（S3）。 通过对光致抗蚀剂进行灰化处理除去光致抗蚀剂，由此露出层间电介质（S4）。 层间电介质通过进行活性氢处理与活化氢接触（S5）。 执行诸如剥离处理的后处理（S6）。 层间电介质由SiOC：H系化合物形成。 活性氢包括氢等离子体。

公开(公告)号：KR1020020004171A

公开(公告)日：2002-01-16

申请号：KR1020000037768

申请日：2000-07-03

Applicant: 삼성전자주식회사

Inventor： 신홍재 ,  구주선

IPC: H01L21/28

CPC classification number: H01L21/76897

Abstract: PURPOSE: A method for forming a contact pad of a semiconductor device is provided to prevent generation of a bridge formed between contact pads by forming an insulating layer having a contact hole. CONSTITUTION: A gate(251) protected by a shield layer(255) is formed on a side and an upper face of a semiconductor substrate(100). A dummy insulating layer is formed to cover a gap between the gates(251). A dummy contact hole is formed by patterning the dummy insulating layer. An interlayer dielectric(500) is formed on the dummy insulating layer in order to fill the dummy contact hole. A planarization process for the interlayer dielectric(500) is performed. A wet etch process for the planarized interlayer dielectric(500) is performed. The dummy insulating layer is removed selectively according to an etch selection ratio. A contact hole(550) is formed on a position of the removed dummy insulating layer. A conductive pad is formed to fill the contact hole(550).

Abstract translation: 目的：提供一种用于形成半导体器件的接触焊盘的方法，以通过形成具有接触孔的绝缘层来防止在接触焊盘之间形成的桥的产生。 构成：在半导体衬底（100）的一侧和上表面上形成由屏蔽层（255）保护的栅极（251）。 形成虚设绝缘层以覆盖栅极（251）之间的间隙。 通过图案化虚拟绝缘层形成虚拟接触孔。 在虚拟绝缘层上形成层间电介质（500），以填充虚拟接触孔。 进行层间电介质（500）的平坦化处理。 进行平面化层间电介质（500）的湿蚀刻工艺。 根据蚀刻选择比选择性地去除虚设绝缘层。 在去除的虚拟绝缘层的位置上形成接触孔（550）。 形成导电垫以填充接触孔（550）。

公开(公告)号：KR100301033B1

公开(公告)日：2001-12-01

申请号：KR1019940033353

申请日：1994-12-08

Applicant: 삼성전자주식회사

Inventor： 신홍재 ,  최지현 ,  황병권

IPC: H01L21/31

Abstract: PURPOSE: A method for fabricating an insulation layer between metallic interconnection patterns is provided to more easily insulate metal interconnection patterns of a semiconductor device by performing a liquid phase deposition(LPD) regarding a substrate to which the metal interconnection pattern is exposed. CONSTITUTION: A metal layer is formed on the substrate(20). A photoresist pattern(24b) is formed on the metal layer. The metal layer is etched to form a metal layer pattern(22a) by using the photoresist pattern as an etch mask. The insulation layer is formed on the substrate where the metal layer pattern and the photoresist pattern are formed. The insulation layer is anisotropically etched to form a spacer insulation layer(26a) on both sidewalls of the metal layer pattern and the photoresist pattern. An insulation layer is formed between the metal layer patterns by an LPD method while using the spacer insulation layer and the photoresist pattern as an oxide barrier layer. The photoresist pattern is eliminated.

公开(公告)号：KR100281891B1

公开(公告)日：2001-04-02

申请号：KR1019940032122

申请日：1994-11-30

Applicant: 삼성전자주식회사

Inventor： 홍창기 ,  김제덕 ,  신홍재 ,  최지현

IPC: H01L21/027

Abstract: 반도체장치의 배선패턴 형성방법이 개시되어 있다. 마스크패턴을 사용하여 감광재료층과 제1배선물질층이 적층되어 있는 기판에 대해 포토에칭을 수행하여 제1배선패턴을 형성하되, 상기 마스크패턴의 패턴간격이 상기 제1배선패턴 배선선폭의 3배가 되도록 하는 한편, 상기 포토에칭시 상기 기판을 상기 제1배선물질층이 적층된 두께만큼 과도식각한다. 다음, 상기 과도식각된 결과물 전면에 균일한 두께의 절연막을 형성하고, 상기 절연막의 상부에 제2배선물질층을 적층한 후, 상기 제2배선물질층을 상기 제1배선패턴의 표면이 드러날 때까지 식각 또는 연마하여 제2배선패턴을 형성한다.

公开(公告)号：KR1020010011118A

公开(公告)日：2001-02-15

申请号：KR1019990030345

申请日：1999-07-26

Applicant: 삼성전자주식회사

Inventor： 구주선 ,  신홍재

IPC: H01L21/28

Abstract: PURPOSE: A forming method is to provide a metal interconnect of a semiconductor device using a low dielectric constant organic dielectric layer with high porosity as an intermetallic insulating layer, thus to prevent a bowing effect and damage of the dielectric layer. CONSTITUTION: A forming method of a metal interconnect comprises the steps of: forming the first metal layer pattern to be connected with a portion of a semiconductor substrate(310); forming an etching barrier layer(340) on the first metal layer pattern; forming an insulating layer pattern on the etching barrier layer in the same size as a via hole to be formed; forming a low dielectric constant organic dielectric layer(380) on the insulating layer pattern; planarizing the dielectric layer to expose the insulating layer pattern; removing the insulating layer pattern to form a via hole for exposing the etching barrier layer; removing the exposed etching barrier layer to form a via hole for exposing the first metal layer pattern; and successively forming a metallic barrier(400) and the second metal layer pattern(410) in the via hole.

Abstract translation: 目的：一种形成方法是使用具有高孔隙率的低介电常数有机电介质层作为金属间绝缘层来提供半导体器件的金属互连，从而防止弯曲效应和电介质层的损坏。 构成：金属互连的形成方法包括以下步骤：形成要与半导体衬底（310）的一部分连接的第一金属层图案; 在所述第一金属层图案上形成蚀刻阻挡层（340）; 在蚀刻阻挡层上形成与要形成的通孔相同尺寸的绝缘层图案; 在所述绝缘层图案上形成低介电常数有机介电层（380）; 平坦化介电层以暴露绝缘层图案; 去除绝缘层图案以形成用于暴露蚀刻阻挡层的通孔; 去除暴露的蚀刻阻挡层以形成用于暴露第一金属层图案的通孔; 并且在所述通孔中依次形成金属阻挡层（400）和所述第二金属层图案（410）。

公开(公告)号：KR100252039B1

公开(公告)日：2000-04-15

申请号：KR1019970051271

申请日：1997-10-06

Applicant: 삼성전자주식회사

Inventor： 최지현 ,  신홍재

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a self-aligned contact hole is provided to suppress a lift-off of an etch stop layer formed on an active region between gate patterns during the formation of an interlayer dielectric layer. CONSTITUTION: In the method, a gate oxide layer(23) is formed on a semiconductor substrate(21), and a plurality of gate patterns(29) are formed in parallel on a defined portion of the gate oxide layer(23). Next, a spacer(31) is formed on a sidewall of each gate pattern(29), and a nitride layer(33) is formed on an exposed portion of the substrate(21) or a possible remainder of the gate oxide layer(23) between the adjacent gate patterns(29). The nitride layer(33) may be formed by a plasma or heat treatment process. The etch stop layer(35) is then formed on a resultant structure including the nitride layer(33), with an improved thickness uniformity due to the nitride layer(33). Next, the interlayer dielectric layer(41) is formed thereon and then planarized. Thereafter, the interlayer dielectric layer(41) is etched to expose the etch stop layer(35) between the adjacent gate patterns(29). After that, by removing the exposed etch stop layer(35) and the underlying nitride layer(33), the self-aligned contact hole is formed.

Abstract translation: 目的：提供一种用于形成自对准接触孔的方法，以抑制在形成层间电介质层期间形成在栅极图案之间的有源区上的蚀刻停止层的剥离。 构成：在该方法中，在半导体基板（21）上形成栅极氧化物层（23），并且在栅极氧化物层（23）的限定部分上平行地形成多个栅极图案（29）。 接下来，在每个栅极图案（29）的侧壁上形成间隔物（31），并且在基板（21）的露出部分或栅极氧化物层（23）的可能剩余部分上形成氮化物层（33） ）在相邻的栅极图案（29）之间。 氮化物层（33）可以通过等离子体或热处理工艺形成。 然后，在包括氮化物层（33）的合成结构上形成蚀刻停止层（35），由于氮化物层（33）而具有改善的厚度均匀性。 接着，在其上形成层间电介质层（41），然后进行平坦化。 此后，蚀刻层间电介质层（41）以露出相邻栅极图案（29）之间的蚀刻停止层（35）。 之后，通过去除暴露的蚀刻停止层（35）和下面的氮化物层（33），形成自对准的接触孔。