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公开(公告)号：KR1019940003331B1
公开(公告)日：1994-04-20
申请号：KR1019910023520
申请日：1991-12-19
Applicant: 한국전자통신연구원
IPC: G06F13/16
Abstract: The method points the bottleneck part in the multiprocessor system, detects the floating point arithmetic and input-output synchronization, and verifies the scheduling equity of operating system and appropriate distribution. The method a employing a system controller (1), a main memory device (2), a processor group (3) and a system bus (4), includes the steps of: load processor generation; completion signal generation; saving and outputting state information; symmetricity determination; and saving and outputting results.
Abstract translation: 该方法指出了多处理器系统中的瓶颈部分，检测浮点算术和输入输出同步，验证了操作系统的调度权益和适当的分配。 采用系统控制器（1），主存储器（2），处理器组（3）和系统总线（4）的方法包括以下步骤：加载处理器生成; 完成信号发生; 保存和输出状态信息; 对称性确定 并保存并输出结果。
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公开(公告)号：KR100352377B1
公开(公告)日：2002-09-11
申请号：KR1019990053513
申请日：1999-11-29
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: 본발명은인텔계열의프로세서와메모리를포함하여구성되는시스템(노드)으로다중노드환경을이루는다중노드시스템에서각 노드들의상태를콘솔스테이션의단일콘솔윈도우에서보여주기위한콘솔구동기운용방법에관한것이다. 다중노드시스템에서사용자는각 노드의운영체제부팅과시스템진단그리고각 노드의상태를보기위해시스템콘솔기능이필요하다. 이를위해본 발명은다중노드시스템을구성하는각 노드의입출력보드에있는 UART(Universal Asynchronous Receiver/Transmitter : 범용비동기송수신기) 칩을이용하여각 노드의 COM1포트와콘솔스테이션의시리얼포트를 RS-232C 케이블로연결한다. 그리고각 노드의시리얼콘솔구동기운용을위한시리얼콘솔구동기초기화, 시리얼콘솔읽기및 시리얼콘솔쓰기를제공함으로써각 노드의상태를콘솔스테이션의단일콘솔윈도우에서보여준다. 본발명은각 노드내의 UART 칩을이용한소프트웨어적인구현이기때문에다중노드시스템에서저 비용으로단일콘솔을가능하게한다. 그리고현재개발중인여러노드가분산공유메모리를이루는분산공유메모리시스템인 CC-NUMA(Cache Coherent-Non Uniform Memory Access) 구조의고성능멀티미디어서버에서도사용가능하다.
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公开(公告)号：KR100331027B1
公开(公告)日：2002-08-13
申请号：KR1019980049406
申请日：1998-11-18
Applicant: 한국전자통신연구원
IPC: G06F9/46
Abstract: 본 발명은 디지털 컴퓨터 시스템에서 단일 신호 인터럽트 방식의 프로세서 (Single Signal Interrupted Processor)로부터 발생한 인터럽트 응답(Interrupt Acknowledge)의 제어에 관련되는 것으로서, 내부에 인터럽트 벡터 레지스터 (Interrupt Vector Register)를 내장한 인터럽트 응답 제어기(Interrupt Acknowledge Controller) 및 그 제어 방법을 제공하는데 그 목적이 있다.
본 발명에 따르면, 단일 신호 인터럽트 방식의 프로세서의 인터럽트 응답 제어 기능을 수행하는 인터럽트 응답 제어기에 있어서, 상기 프로세서의 인터럽트 응답에 대하여 인터럽트 벡터를 제공하고, 상기 프로세서가 읽기 및 쓰기를 수행할 수 있는 인터럽트 벡터 레지스터를 내부에 포함하는 것을 특징으로 하는 인터럽트 응답 제어기가 제공된다.-
Patent Agency Ranking
公开(公告)号：KR1020010063786A
公开(公告)日：2001-07-09
申请号：KR1019990061875
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: PURPOSE: A cache controller having an interrupt controller and a method for controlling an interrupt are provided to control all sorts of interrupts informing all sorts of exceptions generated in a cache control process to a processor promptly and effectively. CONSTITUTION: A node bus interface(210) is connected to a node bus between a node bus being connected to a processor and an interconnection network. An interconnection network interface(220) is connected to the interconnection network. Bus buffers(211, 212, 213, 214) are connected to the node bus interface. Network buffers(221, 222, 223, 224) are connected to the interconnection network interface(220). A cache control logic(200) is connected to the bus buffers(211, 212, 213, 214) and the network buffers(221, 222, 223, 224). A cache(tag memory, data memory) is accessed by the cache control logic(200). An interrupt control unit(230) is connected to the cache control logic(200) and the node bus interface(210) for informing exception contents generated in a cache control process to a processor as an interrupt. The interrupt control unit(230) includes an interrupt control/status register(ICSR)(231) for the interrupt control.
Abstract translation: 目的：提供具有中断控制器和用于控制中断的方法的高速缓存控制器，用于控制各种中断，将快速缓存控制过程中产生的各种异常通知给处理器，并迅速有效地进行处理。 构成：节点总线接口（210）连接到连接到处理器的节点总线和互连网络之间的节点总线。 互连网络接口（220）连接到互连网络。 总线缓冲器（211,212,213,214）连接到节点总线接口。 网络缓冲器（221,222,223,224）连接到互连网络接口（220）。 缓存控制逻辑（200）连接到总线缓冲器（211,212,213,214）和网络缓冲器（221,222,223,224）。 缓存（标签存储器，数据存储器）由高速缓存控制逻辑（200）访问。 中断控制单元（230）连接到高速缓存控制逻辑（200）和节点总线接口（210），用于将高速缓存控制处理中生成的异常内容通知给处理器作为中断。 中断控制单元（230）包括用于中断控制的中断控制/状态寄存器（ICSR）（231）。
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公开(公告)号：KR1020010055958A
公开(公告)日：2001-07-04
申请号：KR1019990057298
申请日：1999-12-13
Applicant: 한국전자통신연구원
IPC: H04L12/00
CPC classification number: G06F15/17337
Abstract: PURPOSE: An apparatus and a method for interconnecting 3-link node and a parallel processing apparatus using the same are provided to obtain an expansion of free nodes using three fixed connection links and implement an easier node divide of 2n number(n>1). CONSTITUTION: Each node(401,402,403,404) includes three fixed connection links, and four nodes form a group(400). A node of the group is a center for connecting the remaining three nodes(402,403,404), and three links(405,408,411) of the center node(401) connect the remaining three nodes(402,403,404). The remaining three nodes(402,403,404) except for the center node(401) have three connection links(405-407,408-410,411-413), and one link(405,408,411) is connected with the center node(401), and remaining two connection links(406,407,409,410,412,413) of three nodes(402,403,404) are used as a connection link of the node group(400). One node group(400) provides two connection links in three nodes and has totally six connection links(406,407,409,410,412,413).
Abstract translation: 目的：提供一种用于互连3链路节点和使用其的并行处理装置的装置和方法，以使用三个固定连接链路来获得对空闲节点的扩展，并实现2n个（n> 1）更容易的节点分割。 构成：每个节点（401,402,403,404）包括三个固定连接链路，四个节点组成一个组（400）。 该组的节点是用于连接剩余的三个节点（402,403,404）的中心，并且中心节点（401）的三个链路（405,408,411）连接剩余的三个节点（402,403,404）。 除了中心节点（401）之外，剩余的三个节点（402,403,404）具有三个连接链路（405-407,408-410,411-413），一个链路（405,408,411）与中心节点（401）连接，剩下的两个连接链路 三个节点（402,403,404）的（406,407,409,410,412,413）被用作节点组（400）的连接链路。 一个节点组（400）在三个节点中提供两个连接链路，共有六个连接链路（406,407,409,410,412,413）。
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公开(公告)号：KR1020000032778A
公开(公告)日：2000-06-15
申请号：KR1019980049354
申请日：1998-11-18
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: PURPOSE: A scheduler and scheduling method of a graphic processor is provided to prevent a deadlock within the graphic processor when a plurality of general processors within a single chip multi processor issue graphic commands to one among the graphic processors so that it can regulate a command issue chance in a low priority general processor. CONSTITUTION: A graphic scheduler comprises tag set logic(51,52,53,54) corresponding to general processors, and a state machine(55). Each tag set logic generates a corresponding tag signal(tag1,tag2,tag3,tag4). For example the tag signal(tag1£2: 0|) comprises input signals, a 1st dispatch signal(dispatch1) and a graphic command signal(Inst1£13: 12|), transmitted from the 1st general processor(GP1). The tag signals is transmitted to the state machine(55), which informs the general processors(GP1,GP2,GP3,GP4) of access preparation for function blocks, GALU(56), GMUL(57), GBMU(58) and GSAD(59) and performs a scheduling operation between the tag signals and the general processors.
Abstract translation: 目的：提供图形处理器的调度器和调度方法，以防止图形处理器内的多个通用处理器在图形处理器之间发出图形命令给图形处理器之间的死锁，从而可以调节命令问题 机会在一个低优先级的通用处理器。 构成：图形调度器包括对应于一般处理器的标签集逻辑（51,52,53,54）和状态机（55）。 每个标签集逻辑生成相应的标签信号（tag1，tag2，tag3，tag4）。 例如，标签信号（tag1£2：0 |）包括从第一通用处理器（GP1）发送的输入信号，第一调度信号（dispatch1）和图形命令信号（Inst1 13：12 |）。 标签信号被发送到状态机（55），其通知功能块的通用处理器（GP1，GP2，GP3，GP4），GALU（56），GMUL（57），GBMU（58）和GSAD （59），并且在标签信号和通用处理器之间执行调度操作。
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公开(公告)号：KR1020000026748A
公开(公告)日：2000-05-15
申请号：KR1019980044409
申请日：1998-10-22
Applicant: 한국전자통신연구원
IPC: H01L21/768
Abstract: PURPOSE: A method for a channel wiring using a horizontal latent reiterated table and a net high and low relationship table is provided to reduce a time for calculation and the number of via by detecting a wiring reiteration and encoding a candidate solution. CONSTITUTION: A method for a channel wiring using a horizontal latent reiterated table and a net high and low relationship table comprises the steps of: encoding candidate solutions representing a solution for a channel wiring; composing a horizontal latent reiterated table and a bet high and low relation ship table from an input net data; composing the candidate solutions; detecting a horizontal reiteration and a vertical reiteration of different nets of the candidate solutions; and generating the candidate solutions and obtaining the solution until the candidate solution not having the reiteration is found.
Abstract translation: 目的：提供一种使用水平潜在重复表和净高低关系表的通道布线的方法，以通过检测布线重复和候选解码的编码来减少计算时间和通孔数。 构成：使用水平潜在重复表和净高低关系表的通道布线的方法包括以下步骤：编码表示用于通道布线的解的候选解; 从输入网络数据构成水平潜在重复表和下注高低关系船表; 撰写候选解决方案; 检测候选解决方案的不同网络的横向重复和垂直重复; 并产生候选解决方案并获得解决方案，直到找到不具有重复的候选解决方案。
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公开(公告)号：KR100250462B1
公开(公告)日：2000-04-01
申请号：KR1019970060662
申请日：1997-11-17
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A method of disassembling and assembling chorus IPC message of Xcent network interface(XNIF) of a high-speed parallel computer is provided to make it easy for the sender to assemble message and for the receiver to disassemble message. CONSTITUTION: In a method of disassembling and assembling chorus IPC message, in step(504), offset value is saved in an offset memory(C_Offset) and a data corresponding to the length of the current message is saved in the message memory(Len). In step(505), the message length of a new offset value is compared to that of the value saved in the offset memory. In step(509), if not, whether the length is longer than 44 is checked. In step(510), if the length is longer than 44, data including LN, Diff bit, XNIF frame offset, stack length, data length, stack length, data length, and remote memory ID value are saved correspondingly. In step(512) the offset value and message length are updated. In step(514), the message is sent through the XNIF. And the process returns to step(505).
Abstract translation: 目的：提供一种拆卸和组装高速并行计算机的Xcent网络接口（XNIF）的合唱IPC消息的方法，使发送方能够方便地组合消息，并使接收方能够拆卸消息。 构成：在拆卸和组装合唱IPC消息的方法中，在步骤（504）中，将偏移量值保存在偏移量存储器（C_Offset）中，并将与当前消息的长度对应的数据保存在消息存储器（Len）中， 。 在步骤（505）中，将新偏移值的消息长度与保存在偏移存储器中的值的消息长度进行比较。 在步骤（509）中，如果不是，则检查长度是否长于44。 在步骤（510）中，如果长度大于44，则相应地保存包括LN，Diff位，XNIF帧偏移，堆栈长度，数据长度，堆栈长度，数据长度和远程存储器ID值的数据。 在步骤（512）中，更新偏移值和消息长度。 在步骤（514）中，消息通过XNIF发送。 并且该过程返回到步骤（505）。
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