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    131.
    发明专利
    未知

    公开(公告)号：DE69630678D1

    公开(公告)日：2003-12-18

    申请号：DE69630678

    申请日：1996-05-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/12 ,  G11C7/00

    Abstract: A column select multiplexer for a memory array organized in modules, each module handling two sets or bunches each of a certain minimum number of bitlines, is realized in a space opposite to the bitlines terminations and the select transistors are realized along a uninterrupted active area strip by realizing isolation gates between adjacent diffusions of two distinct select transistors. The bitlines of the two bunches handled by a multiplexer module are preferably interleaved and the respective select transistors are realized along two parallel uninterrupted active area strips.

    133.
    发明专利
    未知

    公开(公告)号：DE69628729D1

    公开(公告)日：2003-07-24

    申请号：DE69628729

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C5/14 ,  H03K17/22

    Abstract: The circuit (2) includes a generating stage (10) generating a POR pulse; a bump detector (8) detecting bump conditions on the common supply line (6) and enabling the generating stage (10) in the presence of a bump; and a bump supply line (4) connected to a holding capacitor (24) and to the common supply line (6) via an isolation stage (5), which connects the common supply line (6) and the bump supply line (4) in the absence of a bump, and isolates the bump supply line (4) in the presence of a bump. The bump detector (8) is connected to the common supply line (6) and to the bump supply line (4) to generate the POR pulse when the common supply line falls beyond a given level below the voltage of the bump supply line. The circuit is also enabled in the presence of a low supply voltage and when the device is turned off.

    134.
    发明专利
    未知

    公开(公告)号：ITMI20011311A1

    公开(公告)日：2002-12-23

    申请号：ITMI20011311

    申请日：2001-06-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C16/28

    Abstract: A dynamic or non-volatile memory with a differential reading system with improved load rebalancing comprising a rebalancing circuit that for values of the supply and memory selection voltage in excess of a predetermined reference voltage modifies one or the other of two currents, i.e., the measuring current or the reference current, with an equivalent effect on the load rebalancing.

    136.
    发明专利
    未知

    公开(公告)号：DE69622988D1

    公开(公告)日：2002-09-19

    申请号：DE69622988

    申请日：1996-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C15/04 ,  G11C29/00 ,  G06F11/20

    Abstract: A circuit for detecting the coincidence between a binary information unit stored therein and an external datum comprises at least one programmable memory element (MC), a sensing circuit (5) for reading a datum stored in the programmable memory element (MC) and a digital comparator (T1,T2) for comparing the datum stored in the programmable memory element (MC) with the external datum (Ax,An). The sensing circuit (5) comprises a bistable latch having at least one set input (R) coupled to the programmable memory element (MC) and an output (2',2'') suitable to take either one of two logic levels according to a programming state of the programmable memory element, the output (2',2'') supplying directly the digital comparator (T1,T2).

    138.
    发明专利
    未知

    公开(公告)号：DE69618344T2

    公开(公告)日：2002-08-14

    申请号：DE69618344

    申请日：1996-06-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C29/00 ,  G06F11/20

    Abstract: In a memory device equipped with a redundancy circuit comprising at least one redundancy memory register (RR1-RRn) storing a defective address of a defective memory element and an identifying code (OC0-OC3) suitable for identifying a portion of a matrix of memory elements wherein the defective memory element is located, a circuit for transferring redundancy data of a redundancy circuit inside the memory device is provided. The circuit comprises a shared bus (INTBUS) of signal lines (INTBUSm) provided in the memory device to interconnect a plurality of circuit blocks (100,101,8) of the memory device and for transferring signals between the circuit blocks. The shared bus (INTBUS) can be selectively to the various circuit blocks, and a bus assignment circuit (4,7) associated to the redundancy circuit is provided for assigning, during a prescribed time interval of a read cycle of the memory device, the shared bus (INTBUS) to the redundancy circuit whereby in the prescribed time interval the identifying code (OC0-OC3) stored in the redundancy memory register can be transferred onto the shared bus (INTBUS).

    139.
    发明专利
    未知

    公开(公告)号：DE69619501D1

    公开(公告)日：2002-04-04

    申请号：DE69619501

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO ,  ROLANDI PAOLO ,  FONTANA MARCO

    IPC: G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G06F11/20

    Abstract: A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells, which has the particularity that it comprises: at least one bidirectional internal bus (1) for the transfer of data from and to the memory; a redundancy management line (2) that is associated with the internal bus (1); means (8) for enabling/disabling the transmission, over the internal bus (1), of the data from the memory toward the outside; means (11) for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means (5, 12, 13) for enabling/disabling the connection between the outside of the memory and the redundancy line (2) during the reading of the memory matrix and during its programming.

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