公开(公告)号：EP3531228A1

公开(公告)日：2019-08-28

申请号：EP19159837.4

申请日：2019-02-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc. ,  STMicroelectronics (ALPS) SAS

Inventor： POLETTO, Vanni ,  SWANSON, David F ,  TORRISI, Giovanni Luca ,  CHEVALIER, Laurent

IPC: G05F1/56 ,  G05F1/618

Abstract: L'invention concerne un circuit de commande d'au moins deux ensembles (16A, 16B, 16C) de transistors comprenant chacun un premier transistor (1A, 1B, 1C) et un deuxième transistor (2A, 2B, 2C) reliés en série entre des première (15) et deuxième (17) bornes d'alimentation, le courant du point milieu (IoutA, IoutB, IoutC) de chaque ensemble de transistors en série étant régulé selon la différence entre la somme de valeurs représentatives des courants des points milieu de tous les ensembles et la somme de valeurs de consigne (IinA, IinB, IinC) affectées aux ensembles.

公开(公告)号：EP1881635B1

公开(公告)日：2019-08-28

申请号：EP07252871.4

申请日：2007-07-19

Applicant: STMicroelectronics, Inc.

Inventor： Hu, Wendong

IPC: H04B7/26 ,  H04W72/04 ,  H04W16/26 ,  H04W84/04

公开(公告)号：EP2701196A3

公开(公告)日：2017-04-26

申请号：EP13179637.7

申请日：2013-08-07

Applicant: STMicroelectronics, Inc.

Inventor： Liu, Qing ,  Khare, Prasanna ,  Loubet, Nicolas

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/76816 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.

Abstract translation: 一种半导体器件包括其中具有沟道区的半导体衬底，在沟道区上方的栅极结构以及在栅极结构的相对侧上的源极区和漏极区。 各个触点位于每个源极和漏极区域上。 源区和漏区中的至少一个具有与相应触点倾斜的上接触表面。 倾斜的上接触表面比相应的平坦接触表面具有至少大50％的面积。

公开(公告)号：EP2015505A3

公开(公告)日：2016-11-16

申请号：EP08012447.2

申请日：2008-07-10

Applicant: STMicroelectronics Srl ,  STMicroelectronics, Inc.

Inventor： Bertoni, Guido Marco ,  Owen, Jefferson Eugene

IPC: H04L9/06 ,  G09C1/00

CPC classification number: H04L9/0637 ,  G09C1/00 ,  H04L2209/122 ,  H04L2209/125

Abstract: An encoding/decoding apparatus comprises a central processing unit and an encryption/decryption accelerator coupled to the central processing unit The accelerator comprises an input for input data to be encrypted/decrypted, an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data and an output for encrypted/decrypted data coupled to said arithmetic logic unit.

公开(公告)号：EP1471453B1

公开(公告)日：2016-09-28

申请号：EP04252308.4

申请日：2004-04-20

Applicant: STMicroelectronics, Inc.

Inventor： Tamagno, David ,  Tournemille, Jerome

IPC: H04L12/58

CPC classification number: G06F21/606 ,  G06F2221/2153 ,  H04L51/00

公开(公告)号：EP3040888A2

公开(公告)日：2016-07-06

申请号：EP15190240.0

申请日：2015-10-16

Applicant: STMicroelectronics, Inc.

Inventor： BISHT, Chetan ,  SCRIVENER III, Harry

IPC: G06F17/50 ,  H01L27/00

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H03F3/195 ,  H03F3/602 ,  H03K19/017509

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

Abstract translation: 集成电路片上系统（SOC）包括半导体衬底，由形成在衬底中的晶体管构成的多个部件，以及在组件之间提供电连接的多个互连线。 使用无通道设计消除了芯片顶表面上的互连通道。 相反，互连线在金属化的顶层中彼此邻接，从而保留了5-10％的芯片不动产。 通常沿组件之间的互连通道定位的时钟缓冲器位于包含组件的衬底的区域内。 无通道集成电路的设计规则允许馈通互连并排除多扇出互连。

公开(公告)号：EP3026696A1

公开(公告)日：2016-06-01

申请号：EP15185529.3

申请日：2015-09-16

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： FONTANA, Fulvio Vittorio ,  TALLEDO, Jefferson

IPC: H01L21/56 ,  B81B7/00 ,  B81C1/00 ,  H01L23/498

CPC classification number: G01L19/148 ,  B81B7/0045 ,  B81C1/00325 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49575 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: A surface mounting device (50) has one body (6) of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region (15) carrying the body, a cap (20) and contact terminals (3). The base region (15) has a Young's modulus lower than 5 MPa. For forming the device, the body (6) is attached to a supporting frame (1) including contact terminals (3) and a die pad (2), separated by cavities; bonding wires (14) are soldered to the body (6) and to the contact terminals (3); an elastic material is molded so as to surround at least in part lateral sides of the body (6), fill the cavities of the supporting frame (1) and cover the ends of the bonding wires (14) on the contact terminals; and a cap (20) is fixed to the base region (15). The die pad (2) is then etched away.

Abstract translation: 一种表面安装装置（50）具有半导体材料的一个本体（6）：如ASIC，和围绕所述本体的封装件。 所述封装具有承载体上的基极区域（15），盖（20）和接触端子（3）。 基极区域（15）具有的杨氏模量小于5兆帕以下。 为了形成器件，所述主体（6）被附连到支撑框架（1）包括接触端子（3）和所述衬垫（2）中，由空腔分开; 接合线（14）被焊接到所述主体（6）和所述接触端子（3）; 弹性材料被模制，以便至少在所述主体的一部分的横向侧（6），填充所述支撑框架（1）的空腔中并覆盖在接触端子的键合线（14）的端部以包围; 和一个盖（20）被固定到所述基极区域（15）。 所述衬垫（2）随后蚀刻掉。

公开(公告)号：EP2709145A3

公开(公告)日：2016-05-11

申请号：EP13182996.2

申请日：2013-09-04

Applicant: STMicroelectronics, Inc.

Inventor： Zhang, John H

IPC: H01L21/66 ,  B24B37/005 ,  B24B37/04 ,  B24B49/12

CPC classification number: H01L22/12 ,  B24B37/005 ,  B24B37/04 ,  B24B49/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus for performing metrology of a wafer. The apparatus may include a substrate with a plurality of microprobes (520). A plurality of light sources may direct light onto each of the microprobes (520). Light reflected from the microprobes may be detected by a plurality of photodetectors thereby generating a detection signal associated with each of the microprobes. A controller (610)may send a driving signal to each of the plurality of microprobes and determine a height profile and a surface charge profile of the wafer based on each of the detection signals.

公开(公告)号：EP2599111B1

公开(公告)日：2015-09-23

申请号：EP10737725.1

申请日：2010-07-27

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  Stmicroelectronics, Inc.

Inventor： VINET, Maud ,  LIU, Qing

IPC: H01L21/336 ,  H01L21/74 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/743 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L29/41733 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78645 ,  H01L29/78648

公开(公告)号：EP2753148B1

公开(公告)日：2015-09-09

申请号：EP13195746.6

申请日：2013-12-04

Applicant: STMicroelectronics, Inc.

Inventor： Stamm, Thomas

IPC: H02M7/217 ,  H05B33/08

CPC classification number: H02M3/33515 ,  H02M1/42 ,  H02M7/217 ,  H05B33/0815 ,  Y02B20/347

Abstract: A fly-back type switched current regulator includes a primary transformer winding coupled to receive a rectified DC signal derived from an AC signal. The drain of a power transistor is coupled to the primary winding, with the source of the power transistor coupled to an input of a comparison circuit and a primary transformer winding sense resistor. A control terminal of the power transistor is coupled to an output of the comparison circuit. A capacitor stores a variable reference signal for application at a first capacitor terminal to another input of the differential circuit. The variable reference signal is compared to a winding current signal generated by the sense resistor by the comparison circuit. An injection circuit applies an AC signal derived from the rectified DC signal to a second terminal of the capacitor so as to modulate the stored variable reference signal. The regulator is coupled to drive LEDs.