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    Method and apparatus for reducing EMI in a computer system
    132.
    发明授权
    Method and apparatus for reducing EMI in a computer system 有权
    用于在计算机系统中降低EMI的方法和装置

    公开(公告)号：US06219255B1

    公开(公告)日：2001-04-17

    申请号：US09137472

    申请日：1998-08-20

    Applicant: Abeye Teshome

    Inventor： Abeye Teshome

    IPC: H05K111

    CPC classification number: H05K1/0253 ,  H05K1/0216 ,  H05K1/0262 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/10689 ,  Y10T29/49155

    Abstract: A computer system includes a microprocessor, an an input coupled to provide signal inputs to the microprocessor, a mass storage coupled to the microprocessor, a video controller for coupling the microprocessor to a display, a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, and a multilayer printed circuit board for mounting the microprocessor thereon. The multilayer printed circuit board provides for reduced electromagnetic interference (EMI) and includes at least two layers. The multilayer printed circuit board further includes a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein. The second layer is disposed laterally from and substantially parallel to the first layer. The interconnect is further disposed for crossing over the first segment to the second segment in a cross-over region and wherein the first segment and the second segment are further characterized by a secondary gap in the cross-over region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region. A method for reducing a source of EMI in a multilayer printed circuit board is also disclosed.

    Abstract translation: 计算机系统包括微处理器，耦合以向微处理器提供信号输入的输入，耦合到微处理器的大容量存储器，用于将微处理器耦合到显示器的视频控制器，耦合以提供存储以便于执行计算机程序的存储器 以及用于在其上安装微处理器的多层印刷电路板。 多层印刷电路板提供降低的电磁干扰（EMI）并且包括至少两层。 所述多层印刷电路板还包括第一层上的第一导电段，所述第一层上的第二导电区段，所述第二区段通过初级间隙与所述第一区段分离，以及在第二层上的导电互连，所述互连 用于在其中携带高频信号。 第二层从第一层横向设置并基本平行于第一层。 所述互连被进一步布置成用于在交叉区域中跨越所述第一段到所述第二段，并且其中所述第一段和所述第二段的进一步特征在于所述交叉区域中的次级间隙，所述次级间隙小于 用于在交叉区域中提供增加的耦合的主要间隙。 还公开了一种用于减少多层印刷电路板中的EMI源的方法。

    Printed circuit board with noise suppression
    133.
    发明授权
    Printed circuit board with noise suppression 失效
    带噪声抑制的印刷电路板

    公开(公告)号：US06215076B1

    公开(公告)日：2001-04-10

    申请号：US08824798

    申请日：1997-03-26

    Applicant: Hideho Inagawa ,  Toru Otaki

    Inventor： Hideho Inagawa ,  Toru Otaki

    IPC: H01R909

    CPC classification number: H05K1/0216 ,  H05K1/023 ,  H05K1/0233 ,  H05K1/0268 ,  H05K1/0286 ,  H05K3/0005 ,  H05K3/222 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2201/09345 ,  H05K2201/10689 ,  H05K2203/162

    Abstract: Noise frequency generated from a circuit is determined. The distance between two arbitrary lines of a plurality of power feed lines or a plurality of power return lines extending parallel to each other is determined on the basis of the determined noise frequency in question. The distance between jumper lines for bridging the two arbitrary lines is determined on the basis of the noise frequency, thereby suppressing emitted noise which can be generated on a printed circuit board.

    Abstract translation: 确定从电路产生的噪声频率。 基于所确定的噪声频率来确定多个馈电线的两条任意线之间的距离或者彼此平行延伸的多条功率返回线之间的距离。 基于噪声频率确定用于桥接两条任意行的跨接线之间的距离，从而抑制可能在印刷电路板上产生的发射噪声。

    Method and apparatus for clock uncertainty minimization
    134.
    发明授权
    Method and apparatus for clock uncertainty minimization 有权

    公开(公告)号：US6157251A

    公开(公告)日：2000-12-05

    申请号：US439918

    申请日：1999-11-12

    Applicant: Sergio D. Camerlo

    Inventor： Sergio D. Camerlo

    IPC: G06F1/10 ,  H05K1/02 ,  H01L25/00

    CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0231 ,  H05K1/0215 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

    Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

    Thin-film capacitor, multilayer wiring board and semiconductor device
    138.
    发明专利
    Thin-film capacitor, multilayer wiring board and semiconductor device 审中-公开
    薄膜电容器，多层布线板和半导体器件

    公开(公告)号：JP2013008802A

    公开(公告)日：2013-01-10

    申请号：JP2011139836

    申请日：2011-06-23

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： ROKUHARA MASAHITO

    IPC: H01G4/33 ,  H01L23/12 ,  H05K3/46

    CPC classification number: H01G4/33 ,  H01G4/228 ,  H01G4/385 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/162 ,  H05K2201/09345 ,  H05K2201/09663 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a thin-film capacitor, a multilayer wiring board and a semiconductor device which can reduce inductance while suppressing reduction of the effective electrode area, and realize miniaturization.SOLUTION: A thin-film capacitor comprises: plural first capacitative elements each having an electrode layer with a first polarity on an upper surface of a dielectric layer and an electrode layer with a second polarity on a lower surface of the dielectric layer and arranged around a specific position; plural second capacitative elements each having an electrode layer with the second polarity on the upper surface of the dielectric layer and an electrode layer with the first polarity on the lower surface of the dielectric layer and arranged around the specific position alternately with the first capacitative elements; a single common connection hole at the specific position connecting all electrode layers with the first polarity of the first capacitative elements and all electrode layers with the first polarity of the second capacitative elements; and plural individual connection holes around the common connection hole connecting each electrode layer with the second polarity of the first capacitative elements to an electrode layer with the second polarity of the adjacent second capacitative elements.

    Abstract translation: 要解决的问题：提供一种薄膜电容器，多层布线板和半导体器件，其可以在抑制有效电极面积的减小的同时降低电感，并实现小型化。 解决方案：薄膜电容器包括：多个第一电容元件，每个第一电容元件在电介质层的上表面上具有第一极性的电极层和在介电层的下表面上具有第二极性的电极层， 围绕特定位置排列; 多个第二电容元件，每个在电介质层的上表面具有第二极性的电极层，并且在电介质层的下表面上具有第一极性的电极层，并且与第一电容元件交替地布置在特定位置周围; 在特定位置处的单个公共连接孔连接所有电极层与第一电容元件的第一极性和具有第二电容元件的第一极性的所有电极层; 以及将每个电极层与第一电容元件的第二极性连接到具有相邻的第二电容元件的第二极性的电极层的公共连接孔周围的多个单独的连接孔。 版权所有（C）2013，JPO＆INPIT

    Printed circuit board
    139.
    发明专利
    Printed circuit board 有权
    印刷电路板

    公开(公告)号：JP2012069815A

    公开(公告)日：2012-04-05

    申请号：JP2010214397

    申请日：2010-09-24

    Applicant: Canon Inc ,  キヤノン株式会社

    Inventor： MIYAZAKI TOYOHIDE ,  KOYAMA KENJI

    IPC: H05K1/02

    CPC classification number: H05K1/0216 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/14 ,  H05K1/0225 ,  H05K1/0233 ,  H05K1/0243 ,  H05K1/162 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09663 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To reduce radiation noise by suppressing diffusion of noise generated in a circuit element.SOLUTION: A printed circuit board 1 has a power conductor layer 4, a ground conductor layer 3, and a first wiring layer 2 mounted with a semiconductor device 6. An IC feeding section plane 8 is provided in the power conductor layer 4 and is sized to include a range of a projection image of the semiconductor device 6 projected onto the power conductor layer 4. A backbone feeding section plane 7 is provided in the power conductor layer 4 at an interval from the IC feeding section plane 8. The backbone feeding section plane 7 and the IC feeding section plane 8 are connected by connecting wiring 10. A ground plane 11 is provided in the ground conductor layer 3. An opening 12 is formed in a portion of the ground plane 11 overlapping with a projection image of the connecting wiring 10 projected onto the ground conductor layer 3.

    Abstract translation: 要解决的问题：通过抑制在电路元件中产生的噪声的扩散来减少辐射噪声。 解决方案：印刷电路板1具有电源导体层4，接地导体层3和安装有半导体器件6的第一布线层2.IC馈电部分平面8设置在电力导体层4中 并且其尺寸被设计为包括投影到电力导体层4上的半导体器件6的投影图像的范围。主电源导体层平面7以IC间隔从IC馈送部分平面8提供。 主干馈电部分平面7和IC馈送部分平面8通过连接布线10连接。接地平面11设置在接地导体层3中。开口12形成在与投影图像重叠的接地平面11的一部分中 连接布线10投影到接地导体层3上。版权所有（C）2012，JPO＆INPIT

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