公开(公告)号：US5142268A

公开(公告)日：1992-08-25

申请号：US476819

申请日：1990-02-07

Applicant: Nelson T. Clark ,  Dennis Raesner ,  Ronald J. Dedert

Inventor： Nelson T. Clark ,  Dennis Raesner ,  Ronald J. Dedert

IPC: H01C13/02 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16

CPC classification number: H05K1/167 ,  H01C13/02 ,  H05K1/0219 ,  H05K1/141 ,  H05K2201/10045 ,  H05K2203/1572

Abstract: The resistor network of the present invention uses nodal common points with branch conductors for distribution of electrical power to a plurality of resistors. Separating the branch conductors are electromagnetic shields which isolate individual resistors and branch conductors so as to reduce crosstalk between resistors. Additionally, resistors are alternately patterned upon each side of a substrate in order to further reduce crosstalk.

Abstract translation: 本发明的电阻网络使用具有分支导体的节点公共点将功率分配给多个电阻器。 分离导体是电磁屏蔽，隔离各个电阻和分支导体，以减少电阻之间的串扰。 另外，为了进一步减少串扰，电阻器在衬底的每一侧交替地图案化。

公开(公告)号：US20230345627A1

公开(公告)日：2023-10-26

申请号：US17729801

申请日：2022-04-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Fatemeh ZOLFAGHAR ,  Rich Tat AN ,  Bhret Robert GRAYDON

IPC: H05K1/02

CPC classification number: H05K1/0262 ,  H05K2201/10045

Abstract: Techniques and systems for electronic circuit board design is provided herein. An example apparatus comprises an input structure that couples an input voltage node on a circuit board to input nodes of more than one voltage regulator circuit, wherein at least controller footprints differ among each of the more than one voltage regulator circuit. The apparatus further comprises a shared structure that couples switch nodes of the more than one voltage regulator circuit to a first terminal of an inductor footprint common to the more than one voltage regulator circuit, and an output structure that couples a second terminal of the inductor footprint to an output voltage node.

公开(公告)号：US20160211077A1

公开(公告)日：2016-07-21

申请号：US15051648

申请日：2016-02-23

Applicant: ROHM CO., LTD.

Inventor： Hiroki YAMAMOTO ,  Keishi WATANABE ,  Hiroshi TAMAGAWA

IPC: H01G4/30 ,  H01G4/228 ,  H05K1/18 ,  H01G4/005

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232 ,  H01G4/40 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5223 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/101 ,  H01L27/2409 ,  H01L28/40 ,  H01L29/66189 ,  H01L29/94 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/162 ,  H05K1/18 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10045 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

公开(公告)号：US09288908B2

公开(公告)日：2016-03-15

申请号：US14440016

申请日：2013-10-25

Applicant: ROHM CO., LTD.

Inventor： Hiroki Yamamoto ,  Keishi Watanabe ,  Hiroshi Tamagawa

IPC: H01L27/00 ,  H05K1/18 ,  H01L23/522 ,  H01L27/10 ,  H01L27/24 ,  H01G4/40 ,  H01L29/66 ,  H01L29/94 ,  H01G2/06 ,  H05K1/11 ,  H05K1/16 ,  H01G4/30 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232 ,  H01G4/40 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5223 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/101 ,  H01L27/2409 ,  H01L28/40 ,  H01L29/66189 ,  H01L29/94 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/162 ,  H05K1/18 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10045 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Abstract translation: 根据本发明的片状电容器包括衬底，形成在衬底上的一对外部电极，连接在一对外部电极之间的电容器元件和连接在该对外部电极之间并与电容器并联的双向二极管 元件。 此外，根据本发明的电路组件包括根据本发明的片状电容器和具有焊盘焊接到外部电极的焊盘的安装基板，在与衬底的前表面相对的安装表面上。

公开(公告)号：US20140085851A1

公开(公告)日：2014-03-27

申请号：US13626858

申请日：2012-09-25

Applicant: Shawn X. ARNOLD ,  Jeffrey M. THOMA

Inventor： Shawn X. ARNOLD ,  Jeffrey M. THOMA

IPC: H05K7/00 ,  H05K3/32 ,  H05K3/34 ,  H05K1/16

CPC classification number: H05K1/141 ,  H05K1/0231 ,  H05K1/111 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/10045 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49133

Abstract: The described embodiments relate generally to electronic components and more specifically to a capacitor array that can increase component density on a printed circuit board and reduce a distance to a ground plane. An array of capacitors can be formed by coupling a group of capacitors on their sides interspersed with interposer boards. The resulting configuration can increase component density and reduce an amount of resistance and effective series inductance between a set of power decoupling capacitors and an integrated circuit.

Abstract translation: 所描述的实施例一般涉及电子部件，更具体地涉及可以增加印刷电路板上的部件密度并减小到接地平面的距离的电容器阵列。 一组电容器可以通过将一组电容器连接在插入有插入板的侧面上形成。 所得到的配置可以增加组件密度并减少一组功率去耦电容器和集成电路之间的电阻和有效串联电感量。

公开(公告)号：US08493744B2

公开(公告)日：2013-07-23

申请号：US11732543

申请日：2007-04-03

Applicant: Qiang Richard Chen

Inventor： Qiang Richard Chen

IPC: H05K7/00

CPC classification number: H05K3/3442 ,  H01L27/016 ,  H01L27/13 ,  H05K1/16 ,  H05K3/366 ,  H05K3/403 ,  H05K2201/0317 ,  H05K2201/09954 ,  H05K2201/10045 ,  Y02P70/613

Abstract: A device according to various aspects of the present invention generally includes a surface mount device having a top side, a bottom side, a plurality of sidewalls, and a circuit comprising one or more layers. The device includes a first conductive surface covering a portion of one of the sidewalls for providing an input to the circuit, a second conductive surface covering a portion of one of the sidewalls for providing an output from the circuit, and a third conductive surface covering a portion of one of the sidewalls for providing an electrical ground to the circuit. When the surface mount device is mounted to a provided mounting surface, at least one layer of the circuit is orthogonal to the provided mounting surface.

Abstract translation: 根据本发明的各个方面的装置通常包括具有顶侧，底侧，多个侧壁和包括一个或多个层的电路的表面安装装置。 所述装置包括覆盖所述侧壁之一的一部分以提供所述电路的输入的第一导电表面，覆盖所述侧壁之一的一部分以提供来自所述电路的输出的第二导电表面，以及覆盖所述侧壁的第三导电表面 所述侧壁之一的一部分用于向所述电路提供电接地。 当表面安装装置安装到所提供的安装表面时，电路的至少一层与所提供的安装表面正交。

公开(公告)号：US08433839B2

公开(公告)日：2013-04-30

申请号：US13274344

申请日：2011-10-16

Applicant: Zheng-Heng Sun

Inventor： Zheng-Heng Sun

IPC: H05K7/10

CPC classification number: H05K1/029 ,  H05K1/141 ,  H05K2201/09954 ,  H05K2201/10045 ,  H05K2201/10189

Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.

Abstract translation: 连接器组件包括第一至第五连接器，两个PCIe插槽和适配器板。 当第一连接器连接到第五连接器，并且第三连接器连接到第四连接器时，第三连接器的引脚处的信号通过第四连接器传送到第一PCIe插槽的第二组引脚，第五连接器 连接器和串联的第一连接器。 当第二连接器连接到第五连接器，并且第三连接器连接到第四连接器时，通过第四连接器将第三连接器的引脚处的信号传输到第二PCIe插槽的第四组引脚，第五连接器 ，第二连接器串联。

公开(公告)号：US20130042040A1

公开(公告)日：2013-02-14

申请号：US13274344

申请日：2011-10-16

Applicant: ZHENG-HENG SUN

Inventor： ZHENG-HENG SUN

IPC: G06F13/00

CPC classification number: H05K1/029 ,  H05K1/141 ,  H05K2201/09954 ,  H05K2201/10045 ,  H05K2201/10189

Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.

Abstract translation: 连接器组件包括第一至第五连接器，两个PCIe插槽和适配器板。 当第一连接器连接到第五连接器，并且第三连接器连接到第四连接器时，第三连接器的引脚处的信号通过第四连接器传送到第一PCIe插槽的第二组引脚，第五连接器 连接器和串联的第一连接器。 当第二连接器连接到第五连接器，并且第三连接器连接到第四连接器时，通过第四连接器将第三连接器的引脚处的信号传输到第二PCIe插槽的第四组引脚，第五连接器 ，第二连接器串联。

公开(公告)号：US20120147567A1

公开(公告)日：2012-06-14

申请号：US12964503

申请日：2010-12-09

Applicant: Yun-Han Lee ,  Mark Shane Peng ,  Shyh-An Chi

Inventor： Yun-Han Lee ,  Mark Shane Peng ,  Shyh-An Chi

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H01L23/147 ,  H01L23/538 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K2201/10045 ,  H05K2201/10053 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.

Abstract translation: 一种包装结构包括一个包括多个交换机/路由器的联网单元和耦合到该多个交换机/路由器的多个网络接口单元，以及包括多个金属连接的插件。 内插器基本上没有内置的功能元件。 功能元件在插入器之外并且结合到插入器上，其中功能元件通过多个金属连接电耦合到联网单元。

公开(公告)号：US20080303149A1

公开(公告)日：2008-12-11

申请号：US10593535

申请日：2005-01-21

Applicant: Toshiharu Takayama ,  Ryuusuke Suzuki ,  Takefumi Nakamori

Inventor： Toshiharu Takayama ,  Ryuusuke Suzuki ,  Takefumi Nakamori

IPC: H01L23/488

CPC classification number: H01C1/16 ,  H01C1/144 ,  H01C13/02 ,  H01G4/40 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10045 ,  H05K2201/10234 ,  Y02P70/613 ,  H01L2924/00

Abstract: An electronic component including, on one surface of a substrate (1), a plurality of circuit elements and external terminals each consisting of a conductive protrusion (9) for the circuit elements is provided with a structure capable of resisting an external force after mounting. Each of the circuit elements includes, as constituent elements, a pair of electrodes (2) and a resistive element (3) or a dielectric contacting with the pair of electrodes (2), each circuit element is covered with an overcoat (7) while the electrodes (2) are partially exposed as lands (4), the conductive protrusion (9) includes a fixedly bonding member, the conductive protrusion (9) is fixedly bonded to each of the lands (4) by the fixedly bonding member, at least three lands (4b) of the lands (4) are larger in area than the other lands (4a), the electronic component can stand alone while the conductive protrusion (9) contacts with a flat if the conductive protrusion (9) is fixedly bonded only to each of the larger-area lands (4b), and the conductive protrusions are all formed by fixedly bonding conductive balls (10) substantially equal in size to entire surfaces of the respective lands (4).

Abstract translation: 一种电子部件，在基板（1）的一个表面上具有由电路元件用的导电突起（9）构成的多个电路元件和外部端子，其具有能够抵抗安装后的外力的结构。 每个电路元件包括作为组成元件的一对电极（2）和电阻元件（3）或与该对电极（2）接触的电介质，每个电路元件被外涂层（7）覆盖，同时 电极（2）部分地露出为焊盘（4），导电突起（9）包括固定接合部件，导电突起（9）通过固定接合部件固定地接合到每个焊盘（4）上， 如果导电突起（9）固定地，导电突起（9）与平坦接触，则电子部件可以独立地平坦地区域（4）中的至少三个焊盘区域（4b）的面积大于其他焊盘（4a） 仅与每个较大区域焊盘（4b）接合，并且导电突起全部通过将导电球（10）固定地结合到大致相等于各个焊盘（4）的整个表面上而形成。