公开(公告)号：KR1020100011613A

公开(公告)日：2010-02-03

申请号：KR1020080072904

申请日：2008-07-25

Applicant: 삼성전자주식회사

Inventor： 강욱성 ,  정회주 ,  이훈 ,  최장석

IPC: H01L23/12

CPC classification number: H01L2224/16145 ,  H01L2224/16225

Abstract: PURPOSE: A stack memory device for efficiently increasing a memory size, a memory system including the same and a control method thereof are provided to efficiently increase a memory size by including a memory core with a memory cell array in a master chip. CONSTITUTION: One or more master chip(120) includes a first input-output circuit and a first memory core for interfacing with the outside of a memory device. One or more slave chip(130) is accumulated on the upper part of master chips. Each slave chip includes a second memory core. The slave chips are electrically connected each other through first penetrating electrodes(141,142). The slave chips are electrically connected to the master chips through the first penetrating electrodes. The first input-output circuit and the first memory core are formed on the first surface of the master chip. Each slave chip is accumulated on the first surface of master chips.

Abstract translation: 目的：提供一种用于有效提高存储器大小的堆栈存储器件，包括其的存储器系统及其控制方法，以通过在主芯片中包括存储器单元阵列的存储器核心来有效地增加存储器大小。 构成：一个或多个主芯片（120）包括用于与存储器件外部接口的第一输入 - 输出电路和第一存储器核心。 一个或多个从芯片（130）累积在主芯片的上部。 每个从芯片包括第二存储器核心。 从芯片通过第一穿透电极（141,142）彼此电连接。 从芯片通过第一穿透电极电连接到主芯片。 第一输入输出电路和第一存储器核心形成在主芯片的第一表面上。 每个从芯片累积在主芯片的第一表面上。

公开(公告)号：KR1020090055199A

公开(公告)日：2009-06-02

申请号：KR1020070121995

申请日：2007-11-28

Applicant: 삼성전자주식회사

Inventor： 정회주 ,  이정배 ,  이윤상

IPC: G11C29/42

CPC classification number: G11C29/42 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/12015

Abstract: A semiconductor device is provided to extract information required for parity bit generation in response to a continuous decision signal or data masking information, thereby preventing a writing error during continuous writing actions. A memory cell array(201) stores data and parity data. A continuous writing decider(280) decides on identity of a column address in case of a continuous inputting action of a writing command, and generates a continuous decision signal. A parity generator(270) controls generation and output of the current parity data by using previous data and change data in response to the continuous decision signal. The parity generator controls generation and output of the current parity data in response to the continuous decision signal and data masking information.

Abstract translation: 提供半导体器件以响应于连续的判决信号或数据屏蔽信息来提取奇偶校验位生成所需的信息，从而防止连续写入动作期间的写入错误。 存储单元阵列（201）存储数据和奇偶校验数据。 连续写入决定器（280）在写命令的连续输入动作的情况下决定列地址的标识，并生成连续判定信号。 奇偶校验发生器（270）通过使用先前数据来控制当前奇偶校验数据的生成和输出，并且响应于连续判定信号改变数据。 奇偶校验发生器响应于连续判定信号和数据屏蔽信息控制当前奇偶校验数据的产生和输出。

公开(公告)号：KR1020090049290A

公开(公告)日：2009-05-18

申请号：KR1020070115489

申请日：2007-11-13

Applicant: 삼성전자주식회사

Inventor： 장영찬 ,  정회주

IPC: H04B1/38

CPC classification number: H04L25/4917 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/062

Abstract: 멀티 레벨 펄스 진폭 변조 트랜스시버(Multi-level Pulse Amplitude Modulation Transceiver) 및 데이터 송수신 방법이 개시된다. 상기 멀티 레벨 펄스 진폭 변조 트랜스시버는 송신부 및 수신부를 구비할 수 있다. 상기 송신부는 입력 데이터에 응답하여 제 1 내지 제 n 전압 레벨(n은 2
x , x는 2이상의 자연수)의 신호들 중 차동 신호쌍을 출력한다. 상기 수신부는 상기 차동 신호쌍을 수신하고, 상기 수신된 차동 신호쌍 및 상기 차동 신호쌍에 대응하는 기준 신호쌍을 이용하여 데이터를 생성한다. 상기 송신부는 상기 제 k 및 제 k+1 전압 레벨(k는 n/2)간의 전압 차이와 다른 인접한 전압 레벨간의 전압 차이가 상이하도록 조정한다. 상기 멀티 레벨 펄스 진폭 변조 트랜스시버 및 데이터 송수신 방법은 종래보다 적은 개수의 기준 신호를 이용하면서 타이밍 마진(timing margin) 및 전압 마진(voltage margin)을 향상시킬 수 있는 장점이 있다.

公开(公告)号：KR1020090048084A

公开(公告)日：2009-05-13

申请号：KR1020070114292

申请日：2007-11-09

Applicant: 삼성전자주식회사

Inventor： 박문숙 ,  정회주 ,  이정배

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/04

Abstract: 내부 전압 제어 방법 및 그 방법을 이용하는 멀티 칩 패키지 메모리(multi-chip package memory)가 개시된다. 상기 멀티 칩 패키지 메모리는 전달 메모리 칩 및 제 1 내지 제 n 메모리 칩(n은 자연수)을 구비할 수 있다. 상기 전달 메모리 칩은 신호들을 전달하고, 상기 제 1 내지 제 n 메모리 칩은 내부 전압을 발생하여 출력하는 내부 전압 발생 회로를 포함하고 상기 전달 메모리 칩 위에 적층된다. 상기 전달 메모리 칩은 상기 외부에서 수신되는 신호들에 응답하여 상기 각각의 내부 전압을 제어하는 제 1 내지 제 n 제어 신호를 대응하는 메모리 칩으로 출력한다. 상기 내부 전압 제어 방법 및 그 방법을 이용하는 멀티 칩 패키지 메모리는 적층되는 메모리 칩의 크기를 감소시키고 공정을 단순화할 수 있는 장점이 있다.

公开(公告)号：KR1020090037665A

公开(公告)日：2009-04-16

申请号：KR1020070103115

申请日：2007-10-12

Applicant: 삼성전자주식회사

Inventor： 정회주

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1051 ,  G11C5/02 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/2227

Abstract: A memory module is provided to reduce power consumption of 0.2W by byte slice compared with the conventional device by using a single-end signal method. A memory module is composed of 4 byte slice having tow ranks, which includes a plurality of memory device(230,240, 250, 260). The memory module is made of a data chain structure according to the rank. The byte slice is divided by a byte unit. The memory device is composed of a secondary receiver(RxS), a primary receiver(RxP), a secondary transmitter, a primary transmitter, a primary clock receiver, a primary clock transmitter, and PLL(phase Locked Loop).

Abstract translation: 提供了一种存储器模块，通过使用单端信号方法，与常规器件相比，可减少0.2W字节片的功耗。 存储器模块由具有拖尾行列的4字节片组成，包括多个存储器件（230,240,250,260）。 存储器模块由根据等级的数据链结构构成。 字节片除以字节单位。 存储器件由辅助接收器（RxS），主接收器（RxP），次发射器，主发射器，主时钟接收器，主时钟发射器和PLL（锁相环）组成。

公开(公告)号：KR1020080091890A

公开(公告)日：2008-10-15

申请号：KR1020070034901

申请日：2007-04-10

Applicant: 삼성전자주식회사

Inventor： 정회주 ,  이정배

IPC: G11C29/00

CPC classification number: G06F11/1008 ,  G11C5/02 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1045 ,  G11C2029/0411 ,  H04L1/0041 ,  H04L1/0057

Abstract: A semiconductor memory device having an error detection function, a memory system having the semiconductor memory device, and a data output method of the semiconductor memory device are provided to turn off a part of lanes constituting a data frame in response to an error detection enable signal. An error calculator(1200) receives first data from a memory core, and generates error data based on the first data. A serializer(1300) constitutes a first frame based on the first data and the error data in an error detection mode, and generates second data by serializing the first data and the error data according to the first frame, and constitutes a second frame with different shape from the first frame based on the first data in a first operation mode not performing error detection, and generates third data by serializing the first data according to the second frame. An output buffer generates output data by buffering the second data and the third data.

Abstract translation: 提供具有误差检测功能的半导体存储器件，具有半导体存储器件的存储器系统和半导体存储器件的数据输出方法，以便响应于错误检测使能信号来关闭构成数据帧的通道的一部分 。 错误计算器（1200）从存储器核心接收第一数据，并且基于第一数据生成错误数据。 串行器（1300）基于第一数据和错误检测模式中的错误数据构成第一帧，并且通过根据第一帧串行化第一数据和错误数据来生成第二数据，并且构成具有不同的第二帧 在不执行错误检测的第一操作模式下，基于第一数据从第一帧形状，并且通过根据第二帧串行化第一数据来生成第三数据。 输出缓冲器通过缓冲第二数据和第三数据来产生输出数据。

公开(公告)号：KR100809960B1

公开(公告)日：2008-03-07

申请号：KR1020060094704

申请日：2006-09-28

Applicant: 삼성전자주식회사

Inventor： 선우정 ,  이윤상 ,  정회주

IPC: G11C11/401

CPC classification number: G11C11/406 ,  G11C11/40618 ,  G11C8/04 ,  G11C8/12 ,  G11C11/408

Abstract: A refresh circuit of a semiconductor memory device and a refresh method thereof are provided to prevent the increase of refresh time caused by bank group refresh time, when all refresh commands are applied after refresh command of a bank group is applied to the semiconductor memory device. According to a refresh method of a semiconductor memory device comprising a plurality of bank groups having a plurality of banks, refresh is performed for at least one bank. Information of a bank group where the bank of the bank refresh included is stored. An all refresh command to perform refresh for all bank groups after the bank refresh is executed. The information of the bank group stored in the bank group information storing is compared with the information of an initial bank group in the all refresh command applying. If the information of the bank group stored in the bank information does not coincide with the information of the initial bank group, refresh for the initial bank group is performed and then refresh for the other bank groups is performed. Otherwise, refresh for a different bank group from the initial bank group is performed and then refresh for all bank groups is performed.

Abstract translation: 提供了一种半导体存储器件的刷新电路及其刷新方法，以防止在将组组的刷新命令应用于半导体存储器件之后施加所有刷新命令时，由组组刷新时间引起的刷新时间的增加。 根据包括具有多个存储体的多个存储体组的半导体存储器件的刷新方法，对至少一个存储体进行刷新。 存储刷新银行的银行的银行组的信息。 在执行银行刷新后，所有刷新命令用于对所有银行组执行刷新。 存储在银行组信息存储中的银行组的信息与全部刷新命令的应用中的初始银行组的信息进行比较。 如果存储在银行信息中的银行组的信息与初始银行组的信息不一致，则执行初始银行组的刷新，然后执行其他银行组的刷新。 否则，执行与初始银行组的不同银行组的刷新，然后执行所有银行组的刷新。

公开(公告)号：KR100770703B1

公开(公告)日：2007-10-29

申请号：KR1020060082619

申请日：2006-08-30

Applicant: 삼성전자주식회사

Inventor： 최주선 ,  정회주

IPC: G11C5/14

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory system with a power throttling scheme based on a power parameter of a memory device is provided to enable optimum power control by controlling power throttling on the ground of power characteristics information of the memory device. A memory device(200) is set as a specific power characteristics mode through a mode register set command, and provides the set power characteristics information. A memory controller(100) transmits the mode register set command to the memory device, and reads the power characteristics information of the set power characteristics mode, and generates power control information on the ground of the read power characteristics information, and makes a command generation schedule in response to the power control information, and provides a command to the memory device by the command schedule. The memory device comprises a mode register for storing mode setting information, and a power register stored with power characteristics information table on the ground of the mode setting information, and an interface part providing the power characteristics information in response to a power characteristics information request command.

Abstract translation: 提供具有基于存储器件的功率参数的功率节流方案的存储器系统，以通过控制基于存储器件的功率特性信息的功率节流来实现最佳功率控制。 通过模式寄存器设置命令将存储器件（200）设置为特定功率特性模式，并提供设定功率特性信息。 存储器控制器（100）将模式寄存器设置命令发送到存储器件，并读取设置的功率特性模式的功率特性信息，并且基于读取功率特性信息生成功率控制信息，并且产生命令生成 响应于功率控制信息调度，并且通过命令调度向存储器件提供命令。 存储装置包括用于存储模式设置信息的模式寄存器和存储有基于模式设置信息的功率特性信息表的功率寄存器，以及响应于功率特性信息请求命令提供功率特性信息的接口部分 。

公开(公告)号：KR100744130B1

公开(公告)日：2007-08-01

申请号：KR1020060016227

申请日：2006-02-20

Applicant: 삼성전자주식회사

Inventor： 박광수 ,  이재준 ,  김종훈 ,  정회주

IPC: G11C11/4093

Abstract: A termination circuit and a semiconductor memory device comprising the same are provided to improve problems due to the increase of power consumption by periodically controlling whether to enable the termination circuit when a data signal is input. In a termination circuit connected to an input buffer(110) receiving a data signal, at least one termination resistor is connected to the input buffer for impedance matching. At least one switch part controls the connection between the input buffer and the termination resistor. A control signal generation part(140) generates a control signal to control on/off of the switch part. The control signal generation part generates a control signal having a period of 1/n of the data signal input period, and controls the termination circuit to be enabled in a partial period of the data signal input period.

Abstract translation: 提供了一种端接电路和包括该端接电路的半导体存储器件，以通过在输入数据信号时周期性地控制是否使能端接电路来改善由于功耗的增加而导致的问题。 在连接到接收数据信号的输入缓冲器（110）的终端电路中，至少一个终端电阻器连接到输入缓冲器用于阻抗匹配。 至少有一个开关部分控制输入缓冲器和终端电阻之间的连接。 控制信号生成部（140）生成用于控制开关部的接通/断开的控制信号。 控制信号产生部分产生周期为数据信号输入周期的1 / n的控制信号，并且控制终止电路在数据信号输入周期的部分周期中被使能。

公开(公告)号：KR1020070077939A

公开(公告)日：2007-07-30

申请号：KR1020060007852

申请日：2006-01-25

Applicant: 삼성전자주식회사

Inventor： 김석일 ,  한유근 ,  정회주 ,  안영만

IPC: G11C29/00 ,  G11C29/12 ,  G11C5/06

CPC classification number: G11C29/02 ,  G11C5/04 ,  G11C29/025 ,  H05K1/0268 ,  H05K1/181

Abstract: A semiconductor memory module and a semiconductor memory device are provided to perform the test of the memory module easily by enabling to perform an individual signal line short-circuit test for plural semiconductor memory devices without an additional test dedicated pin or an algorithm for test mode entry. A semiconductor memory module comprises a plurality of semiconductor memory devices and a circuit board. The plurality of semiconductor memory devices are installed on the circuit board, and a plurality of first signal lines connected to the semiconductor memory devices in common and a plurality of second signal lines connected to the semiconductor memory devices respectively are arranged on the circuit board. Each of the semiconductor memory devices includes first ports receiving first signals applied from the first signal lines, a second port receiving an enable signal during a test, a signal transmission part transmitting the first signals through the first ports in response to the enable signals, and third ports outputting the first signals transmitted from the signal transmission part and connected to the second signal lines.

Abstract translation: 提供半导体存储器模块和半导体存储器件，以便通过使得能够对多个半导体存储器件执行单独的信号线短路测试来容易地执行存储器模块的测试，而无需附加测试专用引脚或用于测试模式输入的算法 。 半导体存储器模块包括多个半导体存储器件和电路板。 多个半导体存储器件安装在电路板上，并且分别连接到半导体存储器件的多个第一信号线和连接到半导体存储器件的多个第二信号线布置在电路板上。 每个半导体存储器件包括接收从第一信号线施加的第一信号的第一端口，在测试期间接收使能信号的第二端口，响应于使能信号通过第一端口传输第一信号的信号传输部分，以及 第三端口输出从信号传输部分发送并连接到第二信号线的第一信号。