公开(公告)号：KR100419571B1

公开(公告)日：2004-02-19

申请号：KR1020000087031

申请日：2000-12-30

Applicant: 한국전자통신연구원

Inventor： 유병곤 ,  유종선 ,  유인규 ,  이원재 ,  양일석

IPC: G11C11/22

Abstract: PURPOSE: A single transistor ferroelectric memory device is provided, which minimizes a capacitance coupling by reducing a capacitance between adjacent wells, and minimizes an RC delay time by reducing a resistance of the well. CONSTITUTION: A p+ doped layer(402) is formed on an n silicon substrate(401), and a p well(403) is formed thereon. An n+ source/drain(404) is formed on a surface of the p well, and a ferroelectric transistor is constituted by stacking a ferroelectric thin film and a gate electrode on the p well between the source and the drain. And a p+ diffusion layer(408) is formed by being separated from the source/drain by a field oxide(407b) on the surface of the p well. A metal layer(410) is contacted to the n+ source/drain and the p+ diffusion layer through an interlayer insulation film(409) respectively. A trench oxide(411) is formed into a fixed depth of the n silicon substrate by penetrating the p+ doped layer from the surface of the p well. Because a pulse voltage is applied to each port independently by the trench oxide, an electrical disturb from a device array of an adjacent column is prevented during a read/write operation.

Abstract translation: 目的：提供单晶体管铁电存储器件，其通过减小相邻阱之间的电容来最小化电容耦合，并通过减小阱的电阻来最小化RC延迟时间。 构成：在n硅衬底（401）上形成p +掺杂层（402），并在其上形成p阱（403）。 在p阱的表面上形成n +源极/漏极（404），并且通过在源极和漏极之间的p阱上堆叠铁电薄膜和栅电极来构成铁电晶体管。 并且通过在p阱的表面上通过场氧化物（407b）与源极/漏极分离来形成p +扩散层（408）。 金属层（410）分别通过层间绝缘膜（409）与n +源极/漏极和p +扩散层接触。 通过从p阱的表面穿透p +掺杂层，将沟槽氧化物（411）形成为n型硅衬底的固定深度。 由于沟槽氧化物独立地向每个端口施加脉冲电压，因此在读取/写入操作期间防止来自相邻列的器件阵列的电气干扰。

公开(公告)号：KR1020030073224A

公开(公告)日：2003-09-19

申请号：KR1020020012670

申请日：2002-03-09

Applicant: 한국전자통신연구원

Inventor： 유인규 ,  유병곤 ,  이원재 ,  류상욱

IPC: H01L21/8242

Abstract: PURPOSE: A method for etching a thin film and a method for manufacturing a transistor and a capacitor of a semiconductor device using the same are provided to be capable of simplifying manufacturing processes and preventing the damage of a lower layer and the generation of residues by simultaneously patterning a metal thin film and a ferroelectric thin film using a helicon plasma etching process. CONSTITUTION: After forming a lower structure at the upper portion of a semiconductor substrate(201), an SBT(SrxBi1-xTa2O9) thin film(202), a metal thin film(203), and a metal mask(204) are sequentially formed on the resultant structure. Then, the metal thin film and the SBT thin film are simultaneously patterned by carrying out a helicon plasma etching process using the metal mask as an etching mask.

Abstract translation: 目的：提供一种用于蚀刻薄膜的方法以及使用其制造半导体器件的晶体管和电容器的方法，以能够简化制造工艺并防止下层的损坏和同时产生残留物 使用螺旋等离子体蚀刻工艺构图金属薄膜和铁电薄膜。 构成：在半导体基板（201）的上部形成下部结构后，依次形成SBT（SrxBi1-xTa2O9）薄膜（202），金属薄膜（203）和金属掩模（204） 在结果结构上。 然后，通过使用金属掩模作为蚀刻掩模进行螺旋等离子体蚀刻工艺，同时构图金属薄膜和SBT薄膜。

公开(公告)号：KR1020030069242A

公开(公告)日：2003-08-27

申请号：KR1020020008664

申请日：2002-02-19

Applicant: 한국전자통신연구원

Inventor： 류상욱 ,  이원재 ,  유인규 ,  유병곤

IPC: H01L27/10

Abstract: PURPOSE: A ferroelectric device is provided to improve an electrical characteristic of a ferroelectric memory device and a non-cooling infrared sensor using a ferroelectric by forming a bismuth oxide layer having relatively high leakage current through an atomic layer deposition(ALD) method using plasma so that a buffer layer is formed. CONSTITUTION: A lower electrode is formed on a silicon substrate(1). The bismuth oxide layer(15) is formed on the substrate including the lower electrode. A ferroelectric layer(16) is formed on the bismuth oxide layer. An upper electrode is formed on the substrate including the ferroelectric layer.

Abstract translation: 目的：通过使用等离子体的原子层沉积（ALD）方法，通过形成具有相对较高的漏电流的氧化铋层，提供铁电存储器件和使用铁电体的非冷却红外传感器的电特性的铁电体 形成缓冲层。 构成：在硅衬底（1）上形成下电极。 在包括下电极的基板上形成氧化铋层（15）。 在氧化铋层上形成铁电体层（16）。 在包含铁电层的基板上形成上电极。

公开(公告)号：KR100382149B1

公开(公告)日：2003-05-09

申请号：KR1020000072033

申请日：2000-11-30

Applicant: 한국전자통신연구원

Inventor： 이원재 ,  유인규 ,  양일석 ,  유병곤 ,  조경익

IPC: H01L21/31

CPC classification number: H01L21/0228 ,  C23C16/409 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/50 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/02274 ,  H01L21/31691 ,  Y10S438/905

Abstract: An apparatus for forming Strontium-Tantalum-Oxide films and a method thereof using an atomic layer deposition tool are provided. In the Strontium-Tantalum-Oxide films deposited by using plasma and the atomic layer deposition, its leakage-current is very low, and its dielectric constant has a range of 30 to 100 depending on the there heating conditions. Therefore, the method provides structures for i) an insulating film of an NDRO-type ferroelectric memory device that has a structure of Metal-film/Ferroelectric-film/Insulating-film/Silicon, ii) a gate oxide film substituting for silicon oxide film, and iii) an insulating film of Electro Luminescent Display (ELD) device.

Abstract translation: 提供了一种用于形成锶 - 钽 - 氧化物膜的设备及其使用原子层沉积工具的方法。 在通过等离子体和原子层沉积沉积的锶 - 钽 - 氧化物膜中，其泄漏电流非常低，并且其介电常数取决于加热条件在30至100的范围内。 因此，该方法提供了以下结构：i）NDRO型铁电存储器件的绝缘膜，其具有金属膜/铁电膜/绝缘膜/硅的结构，ii）替代氧化硅膜的栅氧化膜 ，和iii）电致发光显示（ELD）装置的绝缘膜。

公开(公告)号：KR100362169B1

公开(公告)日：2002-11-23

申请号：KR1019990044998

申请日：1999-10-18

Applicant: 한국전자통신연구원

Inventor： 조채룡 ,  이원재 ,  유병곤 ,  유인규 ,  김보우

IPC: H01L29/786

Abstract: 본발명은비파괴독출형(Non-destructive read-out type, NDRO) 전계효과트랜지스터및 그제조방법에관한것으로, 특히텅스텐브론즈타입(Tungsten bronze-type)의스트론튬-바륨-나이오븀산화물계 ("SBN") (SrBaNbO)의강유체전박막을유기금속열분해(Metal Organic Decomposition)에의해형성하는방법과이러한방법으로제조된 SBN 박막을게이트유전체로서적용한 NDRO형전계효과트랜지스터및 그제조방법에관한것이다. 본발명은 SBN 박막의물성적인측면에서고온안정성과피로특성을향상시킬수 있는유기금속열분해(MOD : Metal Organic Decomposition) 법에의한 SBN 박막제조방법을제공하는데그 목적이있고, 또한본 발명의다른목적은게이트유전체에 MOD법으로제조된 SBN 박막을적용하고, 산화물전극을졸-겔법(Sol-gel method)에의해형성하여, 강유전성(ferroelectricity)이향상된비파괴독출형(Non-destructive readout-type) 전계효과트랜지스터를제공하는데있다.

公开(公告)号：KR100355267B1

公开(公告)日：2002-10-11

申请号：KR1020000082808

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 유인규 ,  유병곤 ,  이원재 ,  양일석 ,  조경익

IPC: H01L21/336