公开(公告)号：US20090316375A1

公开(公告)日：2009-12-24

申请号：US12457219

申请日：2009-06-04

Applicant: Kouji Ueda

Inventor： Kouji Ueda

IPC: H05K7/06 ,  H05K3/34

CPC classification number: H05K3/3494 ,  H05K1/0206 ,  H05K1/0212 ,  H05K1/111 ,  H05K1/113 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09263 ,  H05K2201/09363 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/099 ,  H05K2201/10015 ,  H05K2201/1003 ,  Y02P70/611 ,  Y10T29/49144

Abstract: An electronic circuit board includes a substrate, a plurality of devices mounted on the substrate, and a pattern part disposed on a surface of the substrate. The devices include a surface mount device having a heat capacity higher than other device. The surface mount device includes a terminal part. The pattern part has an area larger than a pattern area determined in accordance with a current capacity for securing a required current value to be supplied to the surface mount device. The pattern part includes a land part to which the terminal part of the surface mount device is coupled with a solder melted by heating in a reflow furnace.

Abstract translation: 电子电路板包括基板，安装在基板上的多个装置以及设置在基板的表面上的图案部分。 这些装置包括具有高于其它装置的热容量的表面安装装置。 表面安装器件包括端子部件。 图案部分具有大于根据当前容量确定的图案区域的面积，以确保要提供给表面安装装置的所需电流值。 图案部分包括表面安装装置的端子部分与通过在回流炉中加热熔化的焊料耦合的焊盘部分。

公开(公告)号：US07271099B2

公开(公告)日：2007-09-18

申请号：US11146498

申请日：2005-06-06

Applicant: Nigel Ingram Bromley ,  Martin Philip Gouch ,  Christoph Bittner

Inventor： Nigel Ingram Bromley ,  Martin Philip Gouch ,  Christoph Bittner

IPC: H01L21/76

CPC classification number: H05K3/027 ,  H05K3/061 ,  H05K2201/09363 ,  H05K2203/013 ,  H05K2203/1476 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A method of forming a conductive pattern on a substrate. The method comprising providing a substrate carrying a conductive layer; forming a first portion of the conductive pattern by exposing the conductive layer to a laser and controlling the laser to remove conductive material around the edge(s) of desired conductive region(s) of the first portion; and laying down an etch resistant material on the conductive layer, the etch resistant material defining a second portion of the conductive pattern, removing conductive material from those areas of the second portion not covered by the etch resistant material, and then removing the etch resistant material.

Abstract translation: 在基板上形成导电图案的方法。 该方法包括提供承载导电层的衬底; 通过将所述导电层暴露于激光来形成所述导电图案的第一部分，并且控制所述激光以去除所述第一部分的所需导电区域的边缘周围的导电材料; 以及在所述导电层上铺设耐蚀刻材料，所述耐蚀刻材料限定所述导电图案的第二部分，从不被所述耐蚀刻材料覆盖的所述第二部分的那些区域去除导电材料，然后去除所述耐蚀刻材料 。

公开(公告)号：US07256490B2

公开(公告)日：2007-08-14

申请号：US11591744

申请日：2006-11-02

Applicant: Warren M. Farnworth ,  Alan G. Wood

Inventor： Warren M. Farnworth ,  Alan G. Wood

IPC: H01L23/04 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/3128 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2867 ,  H01L21/4846 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0218 ,  H05K1/113 ,  H05K3/027 ,  H05K2201/09363 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A test carrier for a semiconductor component includes a base for retaining the component, and an interconnect on the base having contacts configured to electrically engage component contacts on the component. The base includes conductors in electrical communication with the contacts on the interconnect, which are defined by grooves in a conductive layer. In addition, the conductors include first portions of the conductive layer configured for electrical transmission, which are separated from one another by second portions of the conductive layer configured for no electrical transmission. The test carrier is configured for mounting to a burn in board in electrical communication with a test circuitry configured to apply test signals through the contacts on the interconnect to the component.

公开(公告)号：US20060290374A1

公开(公告)日：2006-12-28

申请号：US11447300

申请日：2006-06-06

Applicant: David Fisher ,  Philip Heft ,  Rocco Vetro

Inventor： David Fisher ,  Philip Heft ,  Rocco Vetro

IPC: G01R31/00

CPC classification number: G09F9/33 ,  G09F9/302 ,  G09F9/3023 ,  H05K1/141 ,  H05K3/321 ,  H05K2201/09227 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2201/2054

Abstract: An alphanumeric display includes a substrate that has top and bottom surfaces, a plurality of electrical contacts on the top surface, a plurality of light-emitting electronic devices mounted on the top surface, and a plurality of electrical pads on the bottom surface. The electrical contacts are connected to at least one light-emitting electronic device, and each of the light-emitting electronic devices is electrically connected with corresponding ones of the electrical contacts. The electrical pads are electrically connected to corresponding ones of the electrical contacts for communicating to the light-emitting electronic devices external sources of electrical power and control signals. The electrical pads on the bottom surface are arranged in a pattern to facilitate connections to the device using a conductive adhesive.

Abstract translation: 字母数字显示器包括具有顶表面和底表面的基板，顶表面上的多个电触点，安装在顶表面上的多个发光电子器件以及底表面上的多个电焊盘。 电触点连接至少一个发光电子器件，并且每个发光电子器件与相应的电触点电连接。 电焊盘电连接到对应的电触头，用于与发光电子设备的外部电源和控制信号源通信。 底表面上的电焊盘以图案布置以便于使用导电粘合剂连接到装置。

公开(公告)号：US20060273069A1

公开(公告)日：2006-12-07

申请号：US11146498

申请日：2005-06-06

Applicant: Nigel Bromley ,  Martin Gouch ,  Christoph Bittner

Inventor： Nigel Bromley ,  Martin Gouch ,  Christoph Bittner

IPC: C23F1/00 ,  B44C1/22 ,  C03C15/00

CPC classification number: H05K3/027 ,  H05K3/061 ,  H05K2201/09363 ,  H05K2203/013 ,  H05K2203/1476 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A method of forming a conductive pattern on a substrate. The method comprising providing a substrate carrying a conductive layer; forming a first portion of the conductive pattern by exposing the conductive layer to a laser and controlling the laser to remove conductive material around the edge(s) of desired conductive region(s) of the first portion; and laying down an etch resistant material on the conductive layer, the etch resistant material defining a second portion of the conductive pattern, removing conductive material from those areas of the second portion not covered by the etch resistant material, and then removing the etch resistant material.

Abstract translation: 在基板上形成导电图案的方法。 该方法包括提供承载导电层的衬底; 通过将所述导电层暴露于激光来形成所述导电图案的第一部分，并且控制所述激光以去除所述第一部分的所需导电区域的边缘周围的导电材料; 以及在所述导电层上铺设耐蚀刻材料，所述耐蚀刻材料限定所述导电图案的第二部分，从不被所述耐蚀刻材料覆盖的所述第二部分的那些区域去除导电材料，然后去除所述耐蚀刻材料 。

公开(公告)号：US06979898B1

公开(公告)日：2005-12-27

申请号：US09420086

申请日：1999-10-18

Applicant: Warren M. Farnworth ,  Alan G. Wood

Inventor： Warren M. Farnworth ,  Alan G. Wood

IPC: H01L21/48 ,  H05K3/02 ,  H01L23/04 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/3128 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2867 ,  H01L21/4846 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0218 ,  H05K1/113 ,  H05K3/027 ,  H05K2201/09363 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor component and a method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The semiconductor component includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.

Abstract translation: 提供了一种半导体元件和用于制造诸如印刷电路板，多芯片模块，芯片级封装和测试载体之类的半导体元件的方法。 半导体部件包括提供其上具有覆盖层的导电层的衬底。 使用激光加工工艺，在导电层中形成凹槽以限定衬底上的导体图案。 导体可以形成为期望的尺寸和间隔，并且可以包括诸如接合焊盘，导电通孔和外部球接触的特征。 此外，所选择的导体可以配置为共面接地或电压迹线，用于调整配置为信号迹线的其他导体中的阻抗值。

公开(公告)号：US6107119A

公开(公告)日：2000-08-22

申请号：US110232

申请日：1998-07-06

Applicant: Warren M. Farnworth ,  Alan G. Wood

Inventor： Warren M. Farnworth ,  Alan G. Wood

IPC: H01L21/48 ,  H05K3/02 ,  H01L21/44 ,  H01L21/50

CPC classification number: H01L23/3128 ,  G01R31/2867 ,  H01L21/4846 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H05K1/0218 ,  H05K3/027 ,  G01R1/0483 ,  G01R3/00 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/72 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/113 ,  H05K2201/09363

Abstract: A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.

Abstract translation: 提供了一种用于制造诸如印刷电路板，多芯片模块，芯片级封装和测试载体的半导体部件的方法。 该方法包括提供其上具有覆盖层的导电层的衬底。 使用激光加工工艺，在导电层中形成凹槽以限定衬底上的导体图案。 导体可以形成为期望的尺寸和间隔，并且可以包括诸如接合焊盘，导电通孔和外部球接触的特征。 此外，所选择的导体可以配置为共面接地或电压迹线，用于调整配置为信号迹线的其他导体中的阻抗值。

公开(公告)号：US4486273A

公开(公告)日：1984-12-04

申请号：US520478

申请日：1983-08-04

Applicant: Joseph P. Lutfy ,  Thaddeus J. Grabowski ,  Robert G. Arnold

Inventor： Joseph P. Lutfy ,  Thaddeus J. Grabowski ,  Robert G. Arnold

IPC: C25D5/02 ,  C25D5/54 ,  H05K3/02 ,  H05K3/10 ,  H05K3/24 ,  C25D5/34

CPC classification number: H05K3/241 ,  C25D5/02 ,  C25D5/54 ,  H05K3/108 ,  H05K2201/09363 ,  H05K3/027 ,  Y10S205/918

Abstract: Process for the maskless electroplating of selective areas of a dielectric substrate comprising depositing an electroconductive film on the surface, evaporating a narrow band of the film off the surface to expose a narrow strip of substrate surrounding a zone of the film where electroplating is unwanted, immersing the substrate in an electroplating bath opposite an appropriate anode, and cathodizing only that portion of the film that covers the region sought to be plated. In one embodiment a laser beam is used to selectively evaporate electroless copper from the surface of an ABS substrate.

Abstract translation: 用于对电介质基底的选择性区域进行无掩膜电镀的方法，包括在表面上沉积导电膜，将膜的窄带从表面蒸发，以暴露围绕电镀区不需要的薄膜区域的窄条带，浸渍 在与适当的阳极相对的电镀槽中的衬底，仅阴极化覆盖寻求镀覆的区域的膜的那部分。 在一个实施例中，激光束用于从ABS衬底的表面选择性地蒸发无电解铜。

公开(公告)号：US3610752A

公开(公告)日：1971-10-05

申请号：US3610752D

申请日：1970-01-15

Applicant: ATOMIC ENERGY COMMISSION

Inventor： WILSON FREDERICK C

IPC: G03F1/00 ,  G03F7/20 ,  H05K3/00 ,  G03B41/00

CPC classification number: G03F7/70058 ,  G03F1/00 ,  G03F7/7035 ,  G03F7/70583 ,  H05K3/0002 ,  H05K2201/09363 ,  H05K2203/056

Abstract: An improved process for preparing printed circuit boards in which only the conductor surrounding the circuitry is removed. A refractor is utilized in preparing the circuit board negative to obtain exposure of the film only in the regions directly adjacent the lines representing the circuitry.

公开(公告)号：KR100988585B1

公开(公告)日：2010-10-18

申请号：KR1020070098061

申请日：2007-09-28

Applicant: 후지쯔 가부시끼가이샤

Inventor： 나카무라나오키 ,  스기노시게루 ,  가나이료

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H05K1/0271 ,  H05K3/28 ,  H05K3/3415 ,  H05K3/3452 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/09363 ,  H05K2201/09781 ,  H05K2203/0588 ,  H05K2203/1572 ,  Y10T29/4913 ,  Y10T29/49147

Abstract: 본 발명은 전자 부품의 단자와 단자 패드의 접속 불량을 확실히 회피할 수 있는 프린트 배선판을 제공하는 것을 과제로 한다.
프린트 배선판(17)에서는, 전자 부품을 수용하는 전자 부품 실장 영역의 뒤쪽에서 특정(特定) 영역(42a∼42d)이 특정된다. 특정 영역(42a∼42d)에서는, 전자 부품 실장 영역으로 규정되는 기판의 표면의 면적 및 도전재의 면적의 비에 따라 도전막(39)이 형성된다. 전자 부품 실장 영역과 특정 영역(42a∼42d)에서 기판(28)의 표면의 면적 및 도전막(39)의 면적의 비가 전자 부품마다 동일해진다. 이와 같이 하여 리플로우(reflow) 공정의 가열 중에 프린트 배선판(17)의 휘어짐은 억제될 수 있다.
특정 영역, 도전막, 단자, 절연막