Abstract:
Provided is an electronic component comprising a first pad row (IPP1-110) having pads extending along corresponding extension lines (L1, L2, L3, L4) and a second pad row (IPP2-110) having pads extending along corresponding extension lines (L10, L20, L30, L40), wherein the pads of the first pad row include first pads (PG1, PG3) and second pads (PG2, PG4), wherein extension lines (L1, L3) of the first pads substantially converge to a first point (P1-1, P3-1), and extension lines (L2, L4) of the second pads substantially converge to a second point (P2-1, P4-1) different from the first point, and wherein the pads of the second pad row include third pads (PG10, PG30) and fourth pads (PG20, PG40), wherein extension lines (L10, L30) of the third pads substantially converge to a third point (P1-2, P3-2), and extension lines of the fourth pads substantially converge to a fourth point (P2-2, P4-2) different from the third point.
Abstract:
The present invention pertains to a submount (1) for mechanically and electrically coupling an electronic component (4) to a carrier (6). The submount (1) has a mounting portion (10) for mounting the submount to the carrier and has attachment portions (12a, 12b, 12c, 12d) for holding the electronic component. The submount further has primary electric contacts (14a, 14b) for cooperation with respective electrical conductors (61a, 61b) in the carrier, and secondary electric contacts (16a, 16b, 16c) for cooperation with respective electric contacts of the electronic component. The secondary electric contacts are electrically connected to primary electric contacts. The attachment portions are coupled to the mounting portion by respective extension portions (18a, 18b, 18c) that are laterally stretchable in a plane defined by the mounting portion to allow a displacement of the attachment portions in a direction away from the mounting portion.
Abstract:
A display panel (110) includes a display configured to display an image by receiving a drive signal, and a pad region including first (PG1, PG3) and second (PG2, PG4) pad groups configured to receive the drive signal from an outside and to provide the received drive signal to the display, wherein the first pad group (PG1, PG3) includes a plurality of first pads extending along a plurality of first imaginary lines (L4), the first imaginary lines being tilted at a predetermined angle with respect to a reference line (RL), wherein the second pad group (PG2, PG4) includes a plurality of second pads extending along a plurality of second imaginary lines (L3), the second imaginary lines being tilted at a predetermined angle with respect to the reference line (RL), and wherein the plurality of first imaginary lines converges into a first point (P1, P3) and the plurality of second imaginary lines converges into a second point (P2, P4), the first and second points being located at different positions.
Abstract:
Disclosed are electrical connectors and methods of assembling an electrical connector having 'standard' (i.e., with electrical contacts having in-line tails), jogged (i.e., with electrical contacts having jogged tails but not connected orthogonally to another connector through a substrate), and/or 'orthogonal' (i.e., with electrical contacts having jogged tails that are used in an orthogonal application) leadframe assemblies in the same connector. This provides the flexibility of using some of the available contacts in an orthogonal application and, at the same time, having remaining contacts available for routing on the midplane PCB. Though this could be done using only orthogonal leadframe assemblies, the combination of standard leadframe assemblies with orthogonal leadframe assemblies creates additional spacing between the PCB vias, so that signal traces can be more easily routed on the midplane PCB.
Abstract:
An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.
Abstract:
A semiconductor device includes a wiring pattern formed on a board, and a semiconductor chip bonded to the wiring pattern by ultrasonic welding. The wiring pattern is formed such that when the semiconductor chip is disposed on the wiring pattern, a range shared between the wiring pattern and positional variation regions of portions to be bonded of the semiconductor chip accompanied by the ultrasonic welding becomes as wide as possible. Such a semiconductor device makes it possible to ensure a sufficient positional deviation range of a wiring pattern with respect to a positional deviation in each bump type electrode, and hence to cope with a multipin structure for flip-chip mounting and to improve both an initial bonding characteristic and a mounting reliability.
Abstract:
A printed circuit board assembly includes two-dimensional arrays of connectors (14,16) to provide significantly higher data transfer rates than typical one-dimensionally arranged connectors, without sacrificing board space. The assembly includes a plurality of connection pads (14,16) on each printed circuit board (10,12). A layer of anisotropically conducting material (26) is placed between the connection pads and the boards are held together by fastening screws (28).