公开(公告)号：EP1227061A2

公开(公告)日：2002-07-31

申请号：EP01127971.8

申请日：2001-11-24

Applicant: ROBERT BOSCH GMBH

Inventor： Fischer, Frank ,  Bischof, Udo ,  Metzger, Lars

IPC: B81B3/00

CPC classification number: B81C1/00896 ,  B81C2201/053

Abstract: Die Erfindung schafft ein Verfahren zum Herstellen eines mikromechanischen Bauelements mit den Schritten: Bereitstellen eines Substrats (1; 2; 4) mit einer Vorderseite und einer Rückseite; Strukturieren der Vorderseite des Substrats (1; 2; 4); zumindest teilweises Abdecken der strukturierten Vorderseite des Substrats (1; 2; 4) mit einer Germanium-enthaltenden Schutzschicht (7; 7'; 7"); Strukturieren der Rückseite des Substrats (1; 2; 4); und zumindest teilweises Entfernen der Germanium-enthaltenden Schutzschicht (7; 7'; 7") von der strukturierten Vorderseite des Substrats (1; 2; 4).

Abstract translation: 本发明提供了用于制造微机械部件，包括以下步骤的方法：提供衬底（1; 2; 4）具有前侧和后侧; 图案化所述基板的前侧（1; 2; 4）; 至少部分地覆盖所述衬底的所述图案化的前侧（1; 2; 4）具有含锗保护层（7; 7“; 7“），图形化所述衬底的背面侧（1; 2; 4）;以及至少部分地去除锗的 含保护层（7; 7“; 7“）通过在衬底的图案化前侧（1; 2; 4）。

公开(公告)号：EP1119032A2

公开(公告)日：2001-07-25

申请号：EP01107622.1

申请日：1993-04-20

Applicant: Denso Corporation

Inventor： Fukada, Tsuyoshi ,  Yoshino, Yoshimi ,  Tanizawa, Yukihiko

IPC: H01L21/306

CPC classification number: B81C1/00888 ,  B81B2201/0235 ,  B81C1/00158 ,  B81C2201/0114 ,  B81C2201/053 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/3063 ,  H01L21/78 ,  Y10S148/028 ,  Y10S148/159 ,  Y10S438/977

Abstract: There is disclosed a method and an apparatus for producing a semiconductor device having a diaphragm in the form of a thin part and an integrated circuit section with electrode on the same substrate, said method comprises a first step of forming a semiconductor layer of a second conduction type over a single-crystal semiconductor substrate of a first conduction type; a second step of forming the integrated circuit section with electrode on the semiconductor layer; a third step of forming the electrode in a scribe line area on the semiconductor layer and electrically connecting the electrode in the scribe line area to the electrode of the integrated circuit section; a fourth step of electrochemically etching predetermined parts of the substrate by transmitting electricity for the electrochemical etching through the electrode in the scribe line area, to form the diaphragm from the semiconductor layer and a fifth step of dicing the substrate into chips along the scribe line area, each of the chips forming the semiconductor device.

Abstract translation: 公开了一种用于制造半导体器件的方法和装置，该半导体器件具有薄膜形式的隔膜和在同一衬底上具有电极的集成电路部分，所述方法包括：形成第二导电半导体层的第一步骤 在第一导电类型的单晶半导体衬底上; 在半导体层上形成具有电极的集成电路部分的第二步骤; 在半导体层上的划线区域中形成电极并将划线区域中的电极与集成电路部分的电极电连接的第三步骤; 通过在划线区域中的电极传输用于电化学蚀刻的电力来电化学蚀刻基板的预定部分，从半导体层形成隔膜的第四步骤，以及沿着划线区域将基板切割成芯片的第五步骤 ，形成半导体器件的每个芯片。

公开(公告)号：EP1111671A2

公开(公告)日：2001-06-27

申请号：EP00127180.8

申请日：2000-12-12

Applicant: Micronas GmbH

Inventor： Igel, Günter, Dipl.-Ing.

IPC: H01L21/78

CPC classification number: B81C1/00904 ,  B81C1/00896 ,  B81C2201/053 ,  H01L21/78 ,  H01L23/3171 ,  H01L2924/0002 ,  Y10S438/928 ,  H01L2924/00

Abstract: Ein Verfahren dient zum Herstellen einer Halbleiteranordnung (3), wobei insbesondere ein Wafer (1) mit einer Vielzahl von Chips (7) bildenden Halbleiteranordnungen hergestellt und der Wafer danach zerteilt und dadurch die Halbleiteranordnungen vereinzelt werden. Zumindest ein Bereich einer Waferseite wird während des Ätzens des übrigen Waferbereichs mittels einer Passivierungsschicht (9) abgedeckt. Nach dem Ätzen wird dann die Passivierungsschicht (9) entfernt.
Zumindest in einem äußeren Randbereich des Wafers, gegebenenfalls zusätzlich im Verlauf der Wafer-Vorderseite, außerhalb der aktiven Chipfläche und insbesondere in den die jeweiligen Chipsysteme umgrenzenden Bereichen werden Haftzonen (8) für die Passivierungsschicht (9) geschaffen, die mit dem für die Passivierungsschicht verwendeten Material eine dichtende, insbesondere chemische Verbindung eingehen.
Außerhalb der Haftzonen ist eine verminderte Haftfähigkeit vorhanden, so dass die Passivierungsschicht (9) zum Beispiel nach dem Rückseitenätzen in dem außerhalb der Haftzonen (8) liegenden Bereich mechanisch durch einen Flüssigkeitsstrom und/oder durch einen Gasstrom und/oder durch Ultraschallbeaufschlagung von der Waferoberfläche entfernt werden kann.

Abstract translation: 一种方法是用于半导体器件（3）的制造方法，特别是晶片（1），具有多个芯片（7）发形成半导体器件，然后将晶片切割并由此分离半导体装置。 至少一个晶片侧的一部分剩余的晶片区域的由钝化层（9）在蚀刻期间被覆盖。 在蚀刻之后，钝化层（9），然后除去。 至少在晶片的外边缘区域，如果合适的话，另外在晶片前侧的过程中，活性的芯片面积之外，并且特别是在其各自的芯片系统边界粘合剂区域（8）的区域被用于在钝化层中创建（9），其连接到用于钝化层的材料 材料接收的密封，特别是化学化合物。 外的键合区，降低密合性存在，使得所述钝化层（9），例如，背面在接合区（8）位于区域通过流机械地除去的外部蚀刻后的液体和/或由气体流和/或通过在晶片表面的超声波处理 可以。

公开(公告)号：EP0983609A1

公开(公告)日：2000-03-08

申请号：EP98925745.6

申请日：1998-05-19

Applicant: THOMSON-CSF SEXTANT

Inventor： LEFORT, OlivierThomson-CSF Protection & Conseil ,  THOMAS, IsabelleThomson-CSF Protection & Conseil

IPC: H01L21/00 ,  G01P15/08

CPC classification number: B81C1/0015 ,  B81B2201/0235 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125

Abstract: The invention concerns the production of machined silicon micro-sensors, in particular accelerometers for assistance to navigation in aircraft, and pressure sensors. In order to improve the production of certain active parts of the sensor, and particularly of a beam (32) forming a resonator, whereof the width and thickness characteristics should be well controlled, the method consists in: producing, by micro-machining the silicon on a first plate (30), a beam with thickness equal to the required final thickness, said beam being coated on its top surface with a mask defining the required final width; assembling the plate (30) with another (10); oxidising the two surfaces of the beam to coat them with a thin protective layer; removing, by vertical directional etching, said thin protective layer on the top surface without removing the mask already there; working on the silicon in the zone exposed by the previous operation, using vertical directional etching on the top surface, until all the part of the beam not protected by the mask is eliminated thereby producing the beam with the required width.

公开(公告)号：EP0684462A2

公开(公告)日：1995-11-29

申请号：EP95106968.1

申请日：1995-05-08

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Hierold, Christofer, Dr.

IPC: G01K7/02 ,  H01L49/00 ,  H01L27/16

CPC classification number: H01L27/16 ,  B81B3/0081 ,  B81B2201/0278 ,  B81B2203/0315 ,  B81C1/00246 ,  B81C1/0069 ,  B81C2201/053 ,  B81C2203/0136 ,  B81C2203/0735 ,  G01F1/6845 ,  G01F1/6888 ,  G01K7/015 ,  G01P15/0802

Abstract: Halbleiterbauelement mit monolithisch integrierten elektronischen Schaltungen und monolithisch integriertem Sensor/Aktuator, bei dem der Sensor/Aktuator mit Methoden des Surface-Micromachining hergestellt ist in einer z. B. mit Sensorstegen (6) strukturierten Sensorschicht (3) aus Polysilizium und diese Sensorstege (6) von einem Siliziumsubstrat (1) durch einen in einer Opferschicht (2) hergestellten und mit einer Verschlußschicht (5) nach außen gasdicht verschlossenen Hohlraum (4) thermisch isoliert sind.

Abstract translation: 具有在其与表面微机械加工的方法中的传感器/致动器的Z制备。B.用传感器腹板（6），被构造传感器层单片集成电子电路和单片集成传感器/致动器的半导体器件（3）的多晶硅和该传感器腹板（6 ）（由制造（在牺牲层2）和（有关闭层5的硅衬底1））（向外气密腔4）是绝热的。

公开(公告)号：EP0683921A1

公开(公告)日：1995-11-29

申请号：EP94903348.0

申请日：1993-12-03

Applicant: CORNELL RESEARCH FOUNDATION, INC.

Inventor： SHAW, Kevin, A. ,  ZHANG, Z., Lisa ,  MACDONALD, Noel, C.

IPC: C23F4 ,  B81B3 ,  G01P15 ,  H01L21 ,  H01L29

CPC classification number: B81C1/00619 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10S73/01 ,  Y10S148/05

Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

公开(公告)号：KR101860210B1

公开(公告)日：2018-05-21

申请号：KR1020160111611

申请日：2016-08-31

Applicant: 가부시기가이샤 디스코

Inventor： 프리바써칼하인츠

IPC: H01L21/02 ,  H01L21/78 ,  H01L21/76 ,  H01L21/56 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L21/78 ,  B81C1/00825 ,  B81C1/00896 ,  B81C2201/053 ,  H01L21/304 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11

Abstract: 발명은일면(1) 상에, 복수의분할선들(11)에의해분할되는복수의디바이스들을갖는디바이스영역(2), 및디바이스영역(2) 주위에형성되고디바이스들을갖지않는주변한계영역(3)을갖는, 웨이퍼프로세싱방법에관한것이며, 여기서디바이스영역(2)은웨이퍼(W)의평면표면으로부터돌출되는복수의돌출부들(14)과함께형성된다. 방법은웨이퍼(W) 상의디바이스들을커버하기위한보호막(4)을웨이퍼(W)의일면(1)에부착하는단계, 및그 전방표면에도포된경화성수지(13)를갖는캐리어(7)를제공하는단계를포함하며, 여기서보호막(4)은접착제를이용하여웨이퍼(W)의일면(1)의적어도일부분에접착된다. 방법은, 웨이퍼(W)의평면표면으로부터돌출되는돌출부들(14)이경화성수지(13)에임베딩되고, 캐리어(7)의전방표면(17)에대향되는캐리어(7)의후방표면(18)이일면(1)에대향되는웨이퍼(W)의면(6)에실질적으로평행하도록, 보호막(4)이부착된웨이퍼(W)의일면(1)을캐리어(7)의전방표면(17)에부착하는단계, 및웨이퍼두께를조정하기위하여일면(1)에대향되는웨이퍼(W)의면(6)을그라인딩하는단계를더 포함한다.

公开(公告)号：KR1020150113146A

公开(公告)日：2015-10-07

申请号：KR1020157023566

申请日：2014-01-15

Applicant: 픽스트로닉스 인코포레이티드

Inventor： 비야레알,자비어 ,  브로스니한,티모시제이. ,  스테인,제스퍼로데윅 ,  페인,리차드에스. ,  레위스,스티븐알.

IPC: B81B3/00 ,  G02B26/02 ,  G09G3/22

CPC classification number: G02B26/02 ,  B81B3/007 ,  B81B2201/045 ,  B81B2203/0163 ,  B81B2203/051 ,  B81C2201/053 ,  B81C2201/112 ,  G02B26/023 ,  G09G3/22

Abstract: 본개시내용은셔터어셈블리를위한비교적보다얇고강성이덜 손실된컴플라이언트빔들을제공하기위한시스템들, 방법들및 장치를제공한다. 보호코팅은셔터어셈블리가희생몰드로부터릴리스되기전에셔터어셈블리위에증착되어패터닝되며, 몰드위에는셔터어셈블리가형성된다. 컴플라이언트빔들의일부주 표면들이희생몰드와접촉하게되기때문에, 이들주 표면들은보호코팅으로코팅되지않는다. 따라서, 셔터어셈블리가최종적으로릴리스될때, 결과적인컴플라이언트빔들은비교적보다얇고강성이덜 손실되어, 셔터어셈블리를동작시키기위하여사용되는작동전압의감소가초래된다. 일부경우들에서, 보호코팅은릴리스전에불연속세그먼트들로패터닝된다.

公开(公告)号：KR1020130023810A

公开(公告)日：2013-03-08

申请号：KR1020110086839

申请日：2011-08-30

Applicant: 한국전자통신연구원

Inventor： 이상균 ,  양일석

IPC: H02N2/18

CPC classification number: B81C1/00682 ,  B81B3/0051 ,  B81C1/0015 ,  B81C2201/0132 ,  B81C2201/053 ,  H01L41/094 ,  H01L41/1134 ,  H01L41/1136 ,  H01M6/40 ,  H01M10/052 ,  H01M10/0585 ,  H02N2/18 ,  H02N2/181 ,  H02N2/188 ,  H03H3/02 ,  H03H3/08 ,  Y02E60/122 ,  Y10T29/42 ,  Y10T29/43

Abstract: PURPOSE: A piezoelectric energy harvesting/ storing device and a manufacturing method thereof are provided to make the resonant frequency of a piezoelectric energy harvesting tuned to the peripheral vibration frequency to reduce an electric loss. CONSTITUTION: A substrate(110) is equipped with a groove on one side of the upper part of the substrate. One end of a piezoelectric MEMS(MicroElectroMechnical Systems) cantilever(120) is fixed on the substrate. The other end of the piezoelectric MEMS cantilever is floated over the upper part of the groove. The piezoelectric MEMS cantilever converts and stores external vibrations. A mass(130) is formed on one end of the piezoelectric MEMS cantilever and adds vibrations to the piezoelectric MEMS cantilever.

Abstract translation: 目的：提供一种压电能量采集/存储装置及其制造方法，以使调谐到周边振动频率的压电能量收集的谐振频率减小电损耗。 构成：衬底（110）在衬底的上部的一侧上配备有凹槽。 压电MEMS（微电子技术系统）悬臂（120）的一端固定在基板上。 压电MEMS悬臂的另一端浮在槽的上部。 压电MEMS悬臂转换并存储外部振动。 在压电MEMS悬臂的一端形成质量块（130），并向压电MEMS悬臂增加振动。

公开(公告)号：KR101201642B1

公开(公告)日：2012-11-14

申请号：KR1020110031730

申请日：2011-04-06

Applicant: 오므론 가부시키가이샤

Inventor： 카사이타카시 ,  이이다노부유키 ,  나카무라토모후미

IPC: H04R19/04 ,  H04R31/00

CPC classification number: B81B7/0016 ,  B81B2201/0257 ,  B81B2207/012 ,  B81C2201/053 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/8592 ,  H01L2924/16151 ,  H04R19/005 ,  H04R31/00 ,  H01L2924/00014

Abstract: This invention aims to protect an outer peripheral part of an upper surface of a silicon substrate with a protective film using a back plate. A conductive diaphragm (33) is arranged on an upper side of a silicon substrate (32) including a back chamber (35), and the diaphragm (33) is supported with an anchor (37). An insulating plate portion (39) is fixed to an upper surface of the silicon substrate (32) so as to cover the diaphragm (33) with a gap. A conductive fixed electrode film (40) is arranged on a lower surface of the plate portion (39) to configure a back plate (34). The change in electrostatic capacitance between the fixed electrode film (40) and the diaphragm (33) is outputted to outside from a fixed side electrode pad (45) and a movable side electrode pad (46) as an electric signal. A protective film (53) is arranged in continuation to the plate portion (39) at an outer periphery of the plate portion (39), which protective film (53) covers the outer peripheral part of the upper surface of the silicon substrate (32) and the outer periphery of the protective film (53) coincides with the outer periphery of the upper surface of the silicon substrate (32).