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公开(公告)号：KR1020050090709A
公开(公告)日：2005-09-14
申请号：KR1020040015915
申请日：2004-03-09
Applicant: 삼성에스디아이 주식회사
IPC: H05B33/06
CPC classification number: G09G3/20 , G09G2300/023 , G09G2300/04 , G09G2320/0233 , G09G2320/0238 , H05K1/0216 , H05K1/0298 , H05K1/0393 , H05K2201/09327
Abstract: 본 발명은 표시장치의 적층구조에 관한 것으로, 상세하게는 아날로그와 디지탈의 출력단 및 접지단을 각각 서로 다른 층에 분리시켜 신호의 간섭에 의한 전도성 노이즈를 방지하는 표시장치의 적층구조에 관한 것이다.
다수개의 스캔신호를 인가하는 스캔드라이버와, 다수개의 데이타신호를 인가하는 데이타드라이버와, 상기 데이타드라이버에 계조전압을 제공하고, 상기 스캔드라이버에 스캔신호를 제공하는 유기전계발광표시장치의 구동장치에 있어서, 상기 유기전계발광표시장치는, 접지층과; 아날로그 신호를 전달하는 아날로그신호전달층과; 디지탈 신호를 전달하는 디지탈신호전달층과; 전원전압을 전달하는 전원전달층이 각각 서로 다른 층에 형성되는 것을 특징으로 한다. 또한, 상기 적층구조는 전면에서 회로구성이 실장되는 제 1 실장층과; 후면에서 회로구성이 실장되는 제 2 실장층을 더 포함한다. 그리고, 상기 적층구조는 각 층간에 형성되어 절연시키는 절연층을 더 포함한다.-
公开(公告)号：KR1020010021267A
公开(公告)日：2001-03-15
申请号：KR1020000046482
申请日：2000-08-11
Applicant: 닛뽕덴끼 가부시끼가이샤
IPC: H05K3/46
CPC classification number: H05K1/0248 , H05K1/0218 , H05K1/0298 , H05K1/162 , H05K2201/09263 , H05K2201/09309 , H05K2201/09327 , H05K2201/10689
Abstract: PURPOSE: To suppress the electromagnetic radiation from electronics by laminating ground layers upon both the top and bottom sides of a power supply layer provided with power supply wiring respectively through first insulating material layers and signal layers provided with signal wiring upon one or both of the top and bottom sides of the power supply layer respectively through second insulating material layers. CONSTITUTION: A multilayered printed board is constituted by successively forming a signal layer 3, a basic insulating material layer 5, a ground layer 2, an power supply insulating material layer 4, and power supply layer 1 from the top side to the bottom side and, under the power supply layer 1, a poser supply insulating material layer 4, a ground layer 2, a basic insulating layer 5, and a signal layer 3 from the top side to the bottom side. In this arrangement, ideal DC power can be apparently individually supplied to circuit elements mounted on the printed board. Therefore, the restrictive factor to the high-speed operations of the circuit elements from a power supply section can be eliminated and, at the same time, the electromagnetic coupling between the power supply line and signal line of the printed board to which high-frequency currents flow and the flowing-out the high-frequency current from the power supply line of the printed board to a power supply cable in a device can be suppressed.
Abstract translation: 目的：通过分别通过第一绝缘材料层和在顶部的一个或两个上设置有信号布线的信号层，将设置有电源布线的电源层的顶层和底侧上的接地层层压在电子线路上以抑制电磁辐射 和电源层的底面分别通过第二绝缘材料层。 构成：多层印刷电路板是从顶侧到底侧连续地形成信号层3，基本绝缘材料层5，接地层2，电源绝缘材料层4和电源层1而构成的， 在电源层1下方，从顶侧到底侧的栅极供给绝缘材料层4，接地层2，基本绝缘层5和信号层3。 在这种布置中，理想的直流电力可以明显地分别提供给安装在印刷电路板上的电路元件。 因此，可以消除来自电源部分的电路元件的高速操作的限制因素，同时，电源线与高频率的印刷电路板的信号线之间的电磁耦合 可以抑制电流的流动以及从印刷电路板的电源线流出到设备中的电源电缆的高频电流。
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公开(公告)号：KR100633062B1
公开(公告)日：2006-10-11
申请号：KR1020040079983
申请日：2004-10-07
Applicant: 삼성전자주식회사
Inventor： 김성기
CPC classification number: H05K1/0216 , H05K1/0298 , H05K2201/0191 , H05K2201/09327
Abstract: 본 발명은 제1 신호층, 접지층, 제2 신호층, 제3 신호층, 전원층 및 제4 신호층을 갖는 6층 인쇄회로기판에 있어서, 상기 제1 신호층과 상기 접지층 사이에 위치하되 그 두께가 0.1mm±0.01mm인 제1 절연층과; 상기 접지층과 상기 제2 신호층 사이에 위치하되 그 두께가 0.15mm±0.015mm인 제2 절연층과; 상기 제2 신호층과 상기 제3 신호층 사이에 위치하되 그 두께가 0.8±0.08mm인 제3 절연층과; 상기 제3 신호층과 상기 전원층 사이에 위치하되 그 두께가 0.15mm±0.015mm인 제4 절연층과; 상기 전원층과 상기 제4 신호층 사이에 위치하되 그 두께가 0.1mm±0.01mm인 제5 절연층을 포함하는 것을 특징으로 한다. 이에 의해, 6층 인쇄회로기판의 다양한 전기적 특성이 동시에 향상시킬 수 있다.
Abstract translation: 本发明位于第一信号层和接地层，和第2信号层，以及所述第三信号层，电源层之间，并具有第四信号层，如权利要求6层印刷电路板，其中所述第一信号层和接地层 厚度为0.1mm±0.01mm的第一绝缘层; 位于接地层和第二信号层之间并具有0.15mm±0.015mm的厚度的第二绝缘层; 位于第二信号层和第三信号层之间并具有0.8±0.08mm厚度的第三绝缘层; 位于第三信号层和电源层之间并具有0.15mm±0.015mm的厚度的第四绝缘层; 并且第五绝缘层位于电源层和第四信号层之间并具有0.1mm±0.01mm的厚度。 因此，可以同时改善六层印刷电路板的各种电特性。
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公开(公告)号：KR1020060031094A
公开(公告)日：2006-04-12
申请号：KR1020040079983
申请日：2004-10-07
Applicant: 삼성전자주식회사
Inventor： 김성기
CPC classification number: H05K1/0216 , H05K1/0298 , H05K2201/0191 , H05K2201/09327
Abstract: 본 발명은 제1 신호층, 접지층, 제2 신호층, 제3 신호층, 전원층 및 제4 신호층을 갖는 6층 인쇄회로기판에 있어서, 상기 제1 신호층과 상기 접지층 사이에 위치하되 그 두께가 0.1mm±0.01mm인 제1 절연층과; 상기 접지층과 상기 제2 신호층 사이에 위치하되 그 두께가 0.15mm±0.015mm인 제2 절연층과; 상기 제2 신호층과 상기 제3 신호층 사이에 위치하되 그 두께가 0.8±0.08mm인 제3 절연층과; 상기 제3 신호층과 상기 전원층 사이에 위치하되 그 두께가 0.15mm±0.015mm인 제4 절연층과; 상기 전원층과 상기 제4 신호층 사이에 위치하되 그 두께가 0.1mm±0.01mm인 제5 절연층을 포함하는 것을 특징으로 한다. 이에 의해, 6층 인쇄회로기판의 다양한 전기적 특성이 동시에 향상시킬 수 있다.
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公开(公告)号：KR100382804B1
公开(公告)日：2003-05-09
申请号：KR1020000046482
申请日：2000-08-11
Applicant: 닛뽕덴끼 가부시끼가이샤
IPC: H05K3/46
CPC classification number: H05K1/0248 , H05K1/0218 , H05K1/0298 , H05K1/162 , H05K2201/09263 , H05K2201/09309 , H05K2201/09327 , H05K2201/10689
Abstract: In order to reduce electromagnetic inductive interference due to power source current, in a multi-layer printed board on which a multiplicity of high-speed and high-frequency circuit elements are mounted, a multi-layer printed board has a construction such that on both upper and lower sides of a power source layer 1 provided with power source wiring 6, are laminated ground layers 2 via respective first insulating material layers 4, and on one or both of the upper and lower sides of these is laminated a signal layer 3 provided with signal wiring, via a second insulating material layer 5.
Abstract translation: 为了减少由于电源电流引起的电磁感应干扰，在其上安装有多个高速和高频电路元件的多层印刷电路板中，多层印刷电路板具有这样的结构， 设置有电源布线6的电源层1的上侧和下侧经由各自的第一绝缘材料层4层压接地层2，并且在它们的上侧和下侧之一或两侧上层压设置有信号层3 通过信号布线，经由第二绝缘材料层5。
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Patent Agency Ranking
公开(公告)号：US20240015897A1
公开(公告)日：2024-01-11
申请号：US18126605
申请日：2023-03-27
Applicant: Samsung Display Co., Ltd.
Inventor： HYO-CHUL LEE , YOUNYEE KANG , JI-WON KIM , SEUNGIN BAEK , IN SOO WANG
CPC classification number: H05K5/0018 , H05K1/189 , H05K5/0086 , H05K2201/10128 , H05K2201/09327
Abstract: A circuit board includes a first body part, a second body part and a connection part. The first body part includes a first contact surface and has a multi-layered structure. The second body part includes a second contact surface, has a multi-layered structure, and includes a first signal line spaced apart from the second contact surface. The connection part includes a third contact surface between the first contact surface and the second contact surface, and connects the first body part and the second body part to each other.
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157.发明申请公开(公告)号：US20180206332A1
公开(公告)日：2018-07-19
申请号：US15923048
申请日：2018-03-16
Applicant: GigaLane Co., Ltd.
Inventor： Sang Pil Kim , Da Yeon Lee , Hwang Sub Koo , Hyun Je Kim , Hee Seok Jung
CPC classification number: H05K1/115 , H05K1/0225 , H05K1/028 , H05K1/0393 , H05K3/0044 , H05K3/4694 , H05K3/4697 , H05K2201/09236 , H05K2201/093 , H05K2201/09327
Abstract: Disclosed is a flexible circuit board having a three-layer dielectric body and four-layer ground layer structure. A flexible circuit board having a three-layer dielectric body and four-layer ground layer structure, according to the present invention, comprises: a first dielectric body; a second dielectric body facing the flat surface of the first dielectric body; a third dielectric body facing the bottom side of the first dielectric body; a signal line formed on the flat surface of the first dielectric body; a pair of first ground layers laminated on the flat surface of the first dielectric body and having the signal line therebetween; second ground layers laminated on the bottom side of the first dielectric body so as to correspond to the first ground layers; a third ground layer laminated on the flat surface of the second dielectric body; and a fourth ground layer laminated on the bottom side of the third dielectric body.
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公开(公告)号：US20180158490A1
公开(公告)日：2018-06-07
申请号：US15823932
申请日：2017-11-28
Applicant: Axis AB
Inventor： Henrik HOVMOLLER
CPC classification number: G11C5/025 , G11C5/04 , G11C5/06 , G11C8/06 , G11C8/12 , H01L27/0207 , H05K1/0243 , H05K2201/09327 , H05K2201/10159 , H05K2201/10545
Abstract: A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed Circuit Board, PCB. A first memory chip (M1) is arranged on a first surface of the PCB, a second memory chip (M2) is arranged on a second surface of the PCB. The second memory chip (M2) is placed back to back to the first memory chip (M1) and oriented such that respective pins having the same function on the first memory chip (M1) and the second memory chip (M2) are placed opposite to each other and connected by vias to respective signal traces arranged between the first and second surfaces of the PCB.
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公开(公告)号：US09520160B2
公开(公告)日：2016-12-13
申请号：US14229483
申请日：2014-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chil-Nam Yoon , Seon-Ryeong Kang , Hui-Chong Shin
CPC classification number: G11C5/06 , G11C7/109 , G11C11/4093 , G11C2207/105 , H05K1/0225 , H05K1/0253 , H05K2201/09327 , H05K2201/10159
Abstract: A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved.
Abstract translation: 存储器模块包括多个半导体存储器件和电路板。 电路板电连接到多个半导体存储器件，信号线设置在电路板的最外层中。 在不与最外层相邻的电路板的层中提供用于信号线的电参考。 因此，可以增加信号线的阻抗，并且可以提高通过信号线传输的信号的信号完整性。
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公开(公告)号：US09401531B2
公开(公告)日：2016-07-26
申请号：US14191595
申请日：2014-02-27
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kanto Iida , Shigeru Tago
CPC classification number: H01P3/08 , H03H7/38 , H05K1/0225 , H05K1/0253 , H05K2201/09327 , H05K2201/09618 , H05K2201/09672 , H05K2201/09727
Abstract: A high-frequency signal transmission line includes a dielectric body including a plurality of dielectric sheets. A signal line is provided in the dielectric body. A connector is mounted on a first main surface of the dielectric body and electrically connected to the signal line. A ground conductor is provided on a second main surface side of the dielectric body, compared with the signal line, and faces the signal line across the dielectric sheet. In the ground conductor, conductor-missing portions are provided in which no conductors are provided in at least portions of regions overlapping with the signal line in planar in connection portions. Adjustment conductors are provided in the second main surface of the dielectric body, and overlap with at least portions of the conductor-missing portions in the planar view.
Abstract translation: 高频信号传输线包括包括多个电介质片的电介体。 信号线设置在电介质体中。 连接器安装在电介质体的第一主表面上并电连接到信号线。 与信号线相比，在电介质体的第二主表面侧设置接地导体，并且面对跨越电介质片的信号线。 在接地导体中，提供导体缺失部分，其中在与连接部分中平面的信号线重叠的区域的至少部分中不设置导体。 调整导体设置在电介质体的第二主表面中，并且在俯视图中与导体缺失部分的至少一部分重叠。
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