公开(公告)号：FR2802706A1

公开(公告)日：2001-06-22

申请号：FR9915838

申请日：1999-12-15

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN

IPC: H05K3/28 ,  H01L21/98 ,  H01L23/522 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/04 ,  H05K3/40 ,  H05K3/46 ,  H01L23/52 ,  H01L21/50 ,  H01L25/00

Abstract: 3D interconnection method of casings or circuits containing electronic components and connecting conductors, where the casings or circuits are stacked in the form of a block (3') by encapsulation by an insulator, involves: (a) the cutting of block by leaving the extremities of conductors (21) indented with respect to corresponding faces (302); (b) the cutting of grooves (40,41) in the faces and perpendicular ones; (c) the metallization of block and the grooves; (d) polishing the faces to remove metallization; (e) encapsulation by resin (303); and (f) metallization of block to ensure shielding (304). The method also includes, in a variant of invention, for supplying power to circuits, a Bus bar, and at step (b) at least one of the grooves cuts into the extremities of two adjacent conductors; the method includes an additional step, that is (g) the cutting of second grooves in the bottom of first grooves in full length, implemented between steps (c) and (e). The width of second grooves is less than that of first grooves. The cutting of grooves is done by sawing, or by use of laser. In another variant of invention, the method comprises an additional step, that is (h) the introduction of a capacitor by bonding plates to lateral faces of groove by a conducting adhesive, which is implemented before step (e). An electronic device with interconnections in three dimensions comprising casings or circuits with connecting conductors and encapsulated to form a block, is made with grooves and metallization according to the method. The metallization is interrupted in full length of second grooves.

公开(公告)号：EP3109899B1

公开(公告)日：2020-03-25

申请号：EP16175880.0

申请日：2016-06-23

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/498 ,  H01L25/10 ,  H05K1/14 ,  H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H05K1/18

公开(公告)号：EP2406815B1

公开(公告)日：2018-07-18

申请号：EP10708971.6

申请日：2010-03-09

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/56 ,  H01L23/00 ,  B81C1/00 ,  H01L23/433 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/4334 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/24137 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

公开(公告)号：EP2368262B1

公开(公告)日：2017-03-08

申请号：EP09797035.4

申请日：2009-12-18

Applicant: 3D Plus

Inventor： VAL, Christian ,  COUDERC, Pascal ,  VAL, Alexandre

IPC: H01L21/60 ,  H01L21/683 ,  H05K3/32 ,  H01L21/56 ,  H05K1/14 ,  H05K1/18

CPC classification number: H01L21/6835 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/141 ,  H05K1/185 ,  H05K3/321 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/0401

公开(公告)号：EP1864326B1

公开(公告)日：2012-11-14

申请号：EP06725523.2

申请日：2006-04-03

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/498 ,  H05K3/34 ,  H01L25/16

CPC classification number: H01L23/4985 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/09663 ,  H05K2203/041 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00

公开(公告)号：EP2126969A1

公开(公告)日：2009-12-02

申请号：EP08708288.9

申请日：2008-01-28

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/60 ,  H01L23/48 ,  H01L25/065 ,  H01L21/98

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16146 ,  H01L2224/81224 ,  H01L2224/8184 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer comprising metallized vias (1) which pass through the thickness of the wafer. The method comprises the following steps of: Depositing a drop (3) of conducting ink containing solvents and nanoparticles of metal onto each via (1) of the first wafer (T1), stacking the second wafer (T2) on the first in such a way that the vias (1) of the second wafer (T2) are substantially overlaid on the vias (1) of the first wafer (T1). Eliminating 50 to 90% of the solvents contained in the drops (3) by heating or vacuum treatment so as to obtain a pasty ink, sintering the drops (3) of pasty ink by laser so as to produce electrical connections (31) between the overlaid metallized vias (1).

公开(公告)号：EP2053646A1

公开(公告)日：2009-04-29

申请号：EP08167277.6

申请日：2008-10-22

Applicant: 3D Plus

Inventor： Val, Christian

IPC: H01L21/48 ,  H01L25/10 ,  H01L21/98

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/351 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: La présente invention concerne un procédé d'interconnexion verticale de n modules électroniques 3D (100), un module comportant un empilement de K tranches électroniques (19) reliées électriquement entre elles par des conducteurs situés selon la direction de l'empilement, qui comprend les étapes consistant à:
A) fabriquer un lot de lagues reconstituées (19) comportant chacune n motifs géométriques délimités par des chemins de découpe (14), chaque motif étant muni d'au moins un composant électronique (6) entouré de résine isolante (9) et connecté à des plots (4) de connexion électrique, les plots étant reliés à des pistes (12) de connexion électrique déposées sur une couche diélectrique (11); chaque piste (12) s'étend jusqu'à une électrode (13) interconnectant les pistes entre elles, et située sur les chemins de découpe (14), et comprend un segment courbe (12a) délimitant une zone (15a) qui entoure un emplacement destiné à former un via,
B) empiler et assembler K lagues reconstituées (19) de manière à superposer lesdites zones (15a),
C) percer des vias (15) dans la résine (9) à l'aplomb des emplacements des vias,
D) métalliser la paroi des vias (15) par croissance électrolytique,
E) découper l'empilement selon les chemins de découpe (14), la largeur de la découpe étant supérieure à celle de l'électrode (13), en vue d'obtenir les modules électroniques 3D (100).

Abstract translation: 该方法包括堆叠晶片（1）以叠加弯曲段的区域，例如 圆弧，电气连接轨道。 通孔沿绝缘树脂穿过层叠方向，并且直接在被区域包围的空间上方形成通孔。 通孔的壁通过电解生长进行金属化。 沿着切割路径切割晶片的堆叠以形成三维电子模块，其中堆叠切割的宽度高于互连轨道的电极的宽度。

公开(公告)号：EP1642336A1

公开(公告)日：2006-04-05

申请号：EP04766105.3

申请日：2004-06-30

Applicant: 3D Plus

Inventor： VAL, Christian THALES Intellectual Property ,  LIGNIER, Olivier THALES Intellectual Property

IPC: H01L23/538 ,  H01L21/98 ,  H01L21/60 ,  H01L21/68

CPC classification number: H01L24/85 ,  H01G4/228 ,  H01G4/40 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: The invention relates to a method for interconnecting thin active and passive composites having two or three dimensions, and to the resulting thin heterogeneous components. According to the invention, the invention involves: the positioning and fixing (11) of at least one active component and one passive component to a supporting surface (23), the contacts being in contact with the support; the deposition (12) of a polymer layer (24) onto the assembly consisting of the support and of these components; the withdrawal (14) of the support; the redistribution of the contacts between the composites and/or toward the periphery by means of metallic conductors (26) arranged according to a predetermined configuration, whereby making it possible to obtain a reconstituted heterogeneous structure; heterogeneous thinning (16) of this structure by non-selective surface finishing of the polymer coating and of at least one passive component (22).

公开(公告)号：EP4533542A1

公开(公告)日：2025-04-09

申请号：EP23725258.0

申请日：2023-05-15

Applicant: 3D Plus

Inventor： LE BLAY, Pierre

IPC: H01L27/146 ,  H01L31/0203

公开(公告)号：EP3261116B1

公开(公告)日：2019-10-02

申请号：EP17175943.4

申请日：2017-06-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/03 ,  H01L21/683