公开(公告)号：WO2005043613A1

公开(公告)日：2005-05-12

申请号：PCT/US2004/035665

申请日：2004-10-27

Applicant: ASM AMERICA, INC. ,  KEETON, Tony, J. ,  GOODMAN, Matthew, G. ,  STAMP, Michael, R.

Inventor： KEETON, Tony, J. ,  GOODMAN, Matthew, G. ,  STAMP, Michael, R.

IPC: H01L21/68

CPC classification number: H01L21/68735 ,  C23C16/4585 ,  H01L21/6833

Abstract: A substrate holder for processing a semiconductor substrate that minimizes substrate non-uniformities as well as backside damage. The substrate holder includes one or more support elements, such as a plurality of veins configured in an annular ring to support an outer edge of a substrate. The veins are configured to support a substrate of a particular size in a support plane defined by the top surfaces of the veins. The substrate holder also has one or more annular grooves formed in the top surface of the holder. In a preferred embodiment, the substrate holder also has a raised annular ring positioned radially inward of the grooves and the support elements. The top surface of the raised annular ring is no higher that the top surfaces of the veins.

Abstract translation: 一种用于处理半导体衬底的衬底保持器，其使衬底不均匀性以及背面损坏最小化。 衬底保持器包括一个或多个支撑元件，例如构造成环形环中的多个静脉，以支撑衬底的外边缘。 静脉构造成在由静脉的顶部表面限定的支撑平面中支撑特定尺寸的基底。 衬底保持器还具有形成在保持器的顶表面中的一个或多个环形槽。 在优选实施例中，衬底保持器还具有位于凹槽和支撑元件的径向内侧的凸起环形环。 凸起环形圈的顶面不大于静脉的顶面。

公开(公告)号：WO2004102648A2

公开(公告)日：2004-11-25

申请号：PCT/US2004/013166

申请日：2004-04-29

Applicant: ASM AMERICA, INC. ,  VERGHESE, Mohith ,  SHERO, Eric, J.

Inventor： VERGHESE, Mohith ,  SHERO, Eric, J.

IPC: H01L21/285

CPC classification number: B82Y30/00 ,  C23C16/403 ,  C23C16/4404 ,  C23C16/45525 ,  C23C22/68 ,  C30B25/14 ,  H01J37/32477

Abstract: Protective layers (208) are formed on a surface (201) of an atomic layer deposition (ALD) or chemical vapor deposition (CVD) reactor (100). Parts defining a reaction space (200) for an ALD or CVD reactor (100) can be treated, in situ or ex situ, with chemicals (206) that deactivate reactive sites (210) on the reaction space surface(s) (201). A pre-treatment step (502) can maximize the available reactive sites (210) prior to the treatment step (504). With reactive sites (210) deactivated by adsorbed treatment reactant (208), during subsequent processing the reactant gases (214) have reduced reactivity or deposition upon these treated surfaces. Accordingly, purge steps (310, 314) can be greatly shortened and a greater number of runs can be conducted between cleaning steps to remove built-up deposition on the reactor walls.

Abstract translation: 在原子层沉积（ALD）或化学气相沉积（CVD）反应器（100）的表面（201）上形成保护层（208）。 可以在原位或非原位处理限定用于ALD或CVD反应器（100）的反应空间（200）的部件与使反应空间表面（201）上的反应位点（210）失活的化学物质（206） 。 预处理步骤（502）可以在处理步骤（504）之前使可用的反应位点（210）最大化。 通过吸附处理反应物（208）使活性位点（210）失活，在随后的处理过程中，反应气体（214）在这些处理过的表面上具有降低的反应性或沉积。 因此，清洗步骤（310,314）可以大大缩短，并且可以在清洁步骤之间进行更多次的运行，以消除反应器壁上的堆积沉积物。

公开(公告)号：WO2004011695A3

公开(公告)日：2004-02-05

申请号：PCT/US2003/023843

申请日：2003-07-29

Applicant: ASM AMERICA, INC. ,  SHERO, Eric, J. ,  GIVENS, Michael, E. ,  SCHMIDT, Ryan

Inventor： SHERO, Eric, J. ,  GIVENS, Michael, E. ,  SCHMIDT, Ryan

IPC: C23C16/448

Abstract: Preferred embodiments of the present invention provides a sublimation system employing guidance structures including certain preferred embodiments having a high surface area support medium (60) onto which a solid source material (7) for vapor reactant is coated. Preferably, a guidance structure is configured to facilitate the repeated saturation of the carrier gas with the solid source for a vapor reactant. Methods of saturating a carrier gas using guidance structures are also provided.

公开(公告)号：WO2003096385A3

公开(公告)日：2003-11-20

申请号：PCT/US2003/014314

申请日：2003-05-07

Applicant: ASM AMERICA, INC.

Inventor： WERKHOVEN, Chris ,  RAAIJMAKERS, Ivo ,  ARENA, Chantal

IPC: H01L27/01

Abstract: Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO 2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.

公开(公告)号：WO2003041124A3

公开(公告)日：2003-05-15

申请号：PCT/US2002/027230

申请日：2002-08-26

Applicant: ASM AMERICA, INC. ,  ASM MICROCHEMISTRY OY ,  HAUKKA, Suvi, P. ,  SHERO, Eric ,  POMAREDE, Chritophe, F. ,  HUBERT MAES, Jan, Willem ,  TUOMINEN, Marko

Inventor： HAUKKA, Suvi, P. ,  SHERO, Eric ,  POMAREDE, Chritophe, F. ,  HUBERT MAES, Jan, Willem ,  TUOMINEN, Marko

IPC: H01L21/28

Abstract: The present invention relates to methods for forming dielectric layers on a substrate, such as in an integrated circuit. In one aspect of the invention, a thin interfacial layer is formed (30). The interfacial layer is preferably an oxide layer and a high-k material is preferably deposited on the interfacial layer by a process that does not cause substantial further growth of the interfacial layer. For example, water vapor may be used as an oxidant source during high-k deposition at less than or equal to about 300°C.

公开(公告)号：WO2003025243A2

公开(公告)日：2003-03-27

申请号：PCT/US2002/029032

申请日：2002-09-10

Applicant: ASM AMERICA, INC. ,  ASM MICROCHEMISTRY OY ,  ELERS, Kai Erik ,  LI, Wei-Min

Inventor： ELERS, Kai Erik ,  LI, Wei-Min

IPC: C23C

CPC classification number: C23C16/45534 ,  C23C16/34 ,  C23C16/36 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24331 ,  H01L2924/00

Abstract: The present methods provide tools for growing conformal metal thin films (150), including metal nitride, metal carbide and metal nitride carbide thin films. In particular, methods are provided for growing such films from aggressive chemicals. The amount of corrosive chemical compounds, such as hydrogen halides, is reduced during the deposition of transition metal, transition metal carbide, transition metal nitride and transition metal nitride carbide thin films on various surfaces, such as metals and oxides. Getter compounds protect surfaces sensitive to hydrogen halides and ammonium halides, such as aluminum, copper, silicon oxide and the layers being deposited, against corrosion. Nanolaminate structures incorporating metallic thin films, and methods for forming the same, are also disclosed.

Abstract translation: 本方法提供用于生长适形金属薄膜（150）的工具，包括金属氮化物，金属碳化物和金属氮化碳薄膜。 特别地，提供了用于从侵蚀性化学品生长这样的膜的方法。 过渡金属，过渡金属碳化物，过渡金属氮化物和过渡金属氮化碳薄膜在各种表面如金属和氧化物的沉积过程中，诸如卤化氢等腐蚀性化合物的量减少。 吸气剂保护对卤化氢和卤化铵敏感的表面，如铝，铜，氧化硅和沉积层，以防腐蚀。 还公开了包含金属薄膜的纳米层压结构及其形成方法。

公开(公告)号：WO2002065517A2

公开(公告)日：2002-08-22

申请号：PCT/US2002/004750

申请日：2002-02-12

Applicant: ASM AMERICA, INC.

Inventor： TODD, Michael, A.

IPC: H01L21/00

CPC classification number: C23C16/0272 ,  B82Y10/00 ,  B82Y30/00 ,  C23C16/22 ,  C23C16/24 ,  C23C16/30 ,  C23C16/308 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/56 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2257 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28194 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/3185 ,  H01L21/32055 ,  H01L28/84 ,  H01L29/127 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/66242 ,  H01L31/1804 ,  H01L31/182 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/933

Abstract: Trisilane is used in chemical vapor deposition methods to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of a heterojunction bipolar transistor, including simultaneous deposition over both single crystal semiconductor surfaces and amorphous insulating regions.

Abstract translation: 三氯硅烷用于化学气相沉积方法以在混合的基底上沉积含硅膜。 这种方法在半导体制造中可用于提供各种优点，包括在异质表面上的均匀沉积，高沉积速率和更高的制造生产率。 例如，形成异质结双极晶体管的基极区域，包括在单晶半导体表面和非晶绝缘区域上的同时沉积。

公开(公告)号：WO2002065510A1

公开(公告)日：2002-08-22

申请号：PCT/US2001/048196

申请日：2001-12-11

Applicant: ASM AMERICA, INC.

Inventor： GOODMAN, Matthew, G.

IPC: H01L21/00

CPC classification number: H01L21/68735 ,  C23C16/4581 ,  C23C16/4584 ,  H01L21/6875

Abstract: An apparatus and method to position a wafer (16) onto a wafer holder (200) and to maintain a uniform wafer temperature is disclosed. The wafer holder or susceptor (200) comprises a recess or pocket (202) whose surface (229) is concave and includes a grid containing a plurality of grid grooves (222) separating protrusions (220). The concavity and grid grooves define an enclosed flow volume (248) between a supported wafer (16) and the susceptor surface, as well as an escape area, or total cross-sectional area of the grid grooves (222) opening out from under the periphery of the wafer (16). These are chosen to reduce the wafer slide and curl during wafer drop-off and wafer stick during wafer pick-up, while improving thermal uniformity and reducing particle problems. In another embodiment, centering locators (250 or 252) in the form of thin, radially placed protrusions are provided around the edge of a susceptor pocket (202) to reduce further the possibility of contact between the wafer and the outer shoulder (206) of the susceptor. These features help to achieve temperature uniformity, and therefore quality of the process result, across the wafer during processing.

Abstract translation: 公开了一种将晶片（16）定位在晶片保持器（200）上并保持均匀晶片温度的装置和方法。 晶片保持器或基座（200）包括其表面（229）是凹形的并包括分隔突起（220）的多个格栅（222）的网格的凹槽（202）。 凹槽和格栅槽限定了支撑晶片（16）和基座表面之间的封闭流体积（248），以及从下面开口的网格槽（222）的逸出区域或总横截面面积 晶片（16）的周边。 这些选择用于在晶片吸收期间在晶片脱落和晶片棒期间减少晶片滑动和卷曲，同时提高热均匀性并减少颗粒问题。 在另一个实施例中，围绕基座凹部（202）的边缘设置呈薄的放射状放置形式的定心定位器（250或252），以进一步减小晶片与外肩部（206）之间的接触的可能性 感受器。 这些特征有助于在加工过程中在晶片上实现温度均匀性，从而达到加工效果的质量。

公开(公告)号：WO2002045167A3

公开(公告)日：2002-06-06

申请号：PCT/US2001/044350

申请日：2001-11-26

Applicant: ASM MICROCHEMISTRY OY ,  ASM AMERICA, INC. ,  HUJANEN, Juha ,  RAAIJMAKERS, Ivo

Inventor： HUJANEN, Juha ,  RAAIJMAKERS, Ivo

IPC: H01L43/12

Abstract: Methods are provided for forming uniformly thin layers in magnetic devices. Atomic layer deposition (ALD) can produce layers that are uniformly thick on an atomic scale. Magnetic tunnel junction dielectrics, for example, can be provided with perfect uniformity in thickness of 4 monolayers or less. Furthermore, conductive layers, including magnetic 12, 16 and non-magnetic layers 14, can be provided by ALD without spiking and other non-uniformity problems. The disclosed methods include forming metal oxide layers by multiple cycles of ALD and subsequently reducing the oxides to metal. The oxides tend to maintain more stable interfaces during formation.

公开(公告)号：WO2010129430A1

公开(公告)日：2010-11-11

申请号：PCT/US2010/033248

申请日：2010-04-30

Applicant: ASM AMERICA, INC. ,  AGGARWAL, Ravinder K. ,  CONNER, Rand

Inventor： AGGARWAL, Ravinder K. ,  CONNER, Rand

IPC: G01K7/02 ,  G01K1/20 ,  G01K1/00 ,  H01L21/66 ,  G05D23/22 ,  G05D23/19

CPC classification number: G01K7/02 ,  G01K1/02 ,  G05D23/1931 ,  G05D23/22

Abstract: A temperature measuring device having a smart chip, or electronic circuit, integrated therein is provided. The smart chip, or electronic circuit, includes at least a unique identification number or data specific to the particular temperature measuring device stored thereon. The electronic circuit further includes calibration data of the temperature measuring device stored thereon. A module controller of a temperature control system is configured to verify the unique identification number of the thermocouple assembly prior to allowing data to be transferred between the temperature measuring device and a temperature controller. A graphical user interface allows an operator to enter the unique identification number or data to verify the temperature measuring device and display an error message if the number or data entered is not equivalent, or does not match, the unique identification number or data stored on the electronic circuit.

Abstract translation: 提供一种具有集成在其中的智能芯片或电子电路的温度测量装置。 智能芯片或电子电路至少包括唯一的识别号码或特定于其上存储的特定温度测量装置的数据。 电子电路还包括存储在其上的温度测量装置的校准数据。 温度控制系统的模块控制器被配置为在允许在温度测量装置和温度控制器之间传送数据之前验证热电偶组件的唯一标识号。 图形用户界面允许操作员输入唯一的标识号或数据来验证温度测量装置，并且如果输入的数字或数据不等同于或不匹配存储在 电子电路。