公开(公告)号：WO1985001172A1

公开(公告)日：1985-03-14

申请号：PCT/US1984001328

申请日：1984-08-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RALLAPALLI, Krishna ,  KAKU, Shinkyo

IPC: H04N01/40

CPC classification number: H04N1/4175 ,  G06T9/005

Abstract: A method and device for two-dimensionally coding digital facsimile signals, especially for the CCITT T.4 recommended standard. A line of digitized picture elements is coded with respect to a reference line of digitized picture elements. The run lengths of color units previous to color change picture elements in the coding and reference lines are accumulated, and the positions of the color change picture elements in the coding line with respect to the positions of the color change picture elements in the reference line are determined by the differences between the accumulated run lengths of the coding and reference line color change picture element and the reference line color change picture elements. The steps are selectively repeated in predetermined sequences responsive to the value of the accumulated run length differences. The present invention also provides for a facsimile device which has control logic (600) for controlling the operations of the device, accumulated run length generator block (120) sequentially generates accumulated run lengths of each change picture element in the coding line and reference line, logic (502) for determining the differences in the accumulated run lengths of coding and reference line picture elements and an encoder (502) for encoding the difference in accordance with a predetermined code, whereby the control logic (600) responsive to the differences, selectively advances the generators for the accumulated run lengths of the next coding line and reference line change picture elements.

公开(公告)号：WO1985001171A1

公开(公告)日：1985-03-14

申请号：PCT/US1984001327

申请日：1984-08-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RALLAPALLI, Krishna ,  KAKU, Shinkyo

IPC: H04N01/40

CPC classification number: H03M7/46 ,  G06T9/005 ,  H04N1/419

Abstract: A high speed facsimile device suitable for integration using present day VLSI technology, for encoding binarily digitized picture information into run length codes. The device receives consecutive blocks of digitized picture data. In the device a run length generator unit (30), which is responsive to these consecutive blocks of picture data, generates the run lengths of color units in a data block. A combining unit (13) coupled to the run length generator unit (30) combines the run lengths of color units in more than one data block and an encoding unit (15) coupled to the run length generator unit (30) via the combining unit (13) generates in a pre-determined code, such as the recommended CCITT T.4 standard, the coded run lengths of color units independent of the data blocks.

公开(公告)号：WO1985001166A1

公开(公告)日：1985-03-14

申请号：PCT/US1984001427

申请日：1984-09-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  VARADARAJAN, Hemmige, D.

IPC: H03K19/086

CPC classification number: H03K19/086 ,  H03K19/013

Abstract: The reference portion of a primitive current switch (QA, QB, and QR) used in emitter coupled logic or current mode logic is modified by introducing a slow device (QRR) as the reference element in order to enhance the speed of turn on and turn off of the input elements (QA and QB). In particular, the reference transistor (QR) of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode (QRR) in order to bypass the emitter dynamic resistance. The emitter time constant of the reference QR is thereby increased so that the voltage on the common source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor QA is switched on or off significantly faster.

Abstract translation: 在发射极耦合逻辑或电流模式逻辑中使用的原始电流开关（QA，QB和QR）的参考部分通过引入慢速装置（QRR）作为参考元件来修改，以提高打开和转动速度 关闭输入元素（QA和QB）。 特别地，为了绕过发射极动态电阻，常规ECL反相器门或常规CML反相器门的参考晶体管（QR）被替换为慢晶体管或慢二极管（QRR）。 因此，参考QR的发射器时间常数增加，使得当输入元件的基极瞬时改变时，公共源节点（节点3）上的电压基本上不变化。 因此，诸如晶体管QA的输入元件的集电极输出明显更快地被接通或断开。

公开(公告)号：WO1985000941A1

公开(公告)日：1985-02-28

申请号：PCT/US1984001241

申请日：1984-08-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CAMPBELL, David, L.

IPC: H03B05/02

CPC classification number: H03K3/0315 ,  H03K3/70 ,  H03K9/06 ,  H03K2005/00097 ,  H03K2005/00176 ,  H03L7/07 ,  H03L7/0995 ,  Y10S331/03

Abstract: As shown in (Fig. 2A), the fall time of an ECL gate (20) is precisely controlled using a fixed capacitor (46) which is connected between the positive supply voltage and the ECL gate output terminal (44), and a variable current source (48, 50, 52) connected between ground (GRND 3) and the ECL gate output terminal (44). A time-delay circuit is obtained by controlling the variable current source with an error voltage (VR2) of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates (12, 14, 16), as shown Fig. 1, with controlled fall times in a ring oscillator configuration. Addition of a noninverting input (19) to one ECL gate (16) makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided, as shown in Figs. 5A and 5B, by phase-locking the output signal of a first phase-locked loop (130) to a system reference signal (TCK) to generate a first-loop control voltage (X4). A second phase-locked loop is phase-locked to the received signal (MNCK) with a second-loop control voltage (VR4). In addition, the second phase-locked loop (142) is also frequency-locked to the system reference signal (TCK) by the first-loop control voltage (X4). This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

Abstract translation: 如图2A所示，使用连接在正电源电压和ECL门输出端子（44）之间的固定电容器（46）精确地控制ECL门（20）的下降时间，并且可变 连接在地（GRND 3）和ECL门输出端（44）之间的电流源（48,50,52）。 通过以锁相环的误差电压（VR2）控制可变电流源，使得时间延迟精确地跟踪用于锁相环的参考信号的频率来获得延时电路。 通过组合时间延迟电路获得信号检测器电路。 通过连接3个ECL门（12,14,16）来组装压控振荡器，如图1所示。 1，具有环形振荡器配置中受控的下降时间。 将一个非反相输入（19）添加到一个ECL门（16）使得压控振荡器可中断。 将所描述类型的压控振荡器与由参考信号馈送的相位检测器相结合，提供锁相环，其控制电压提供频率 - 电压转换功能。 提供了一种从接收信号提供接收机时钟参考信号的系统，如图1和2所示。 参考图5A和5B，通过将第一锁相环（130）的输出信号相互锁定到系统参考信号（TCK）以产生第一回路控制电压（X4）。 第二个锁相环与具有第二回路控制电压（VR4）的接收信号（MNCK）锁相。 此外，第二锁相环（142）也通过第一回路控制电压（X4）而被频率锁定到系统参考信号（TCK）。 该系统对于从曼彻斯特编码的信号恢复接收机时钟参考特别有用。

公开(公告)号：WO1985000468A1

公开(公告)日：1985-01-31

申请号：PCT/US1984001106

申请日：1984-07-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  THOMPSON, Michael, D.

IPC: H01L27/02

CPC classification number: H01L27/11898 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die (10) including a core cell (14) for processing signals, a plurality of bonding pads (18) positioned about the core cell (14), and a plurality of undedicated interface cells (16) for either inputting the signals from the bonding pads (18) to the core cell (14) or outputting the signals from the core cell (14) to the bonding pads (18), including a plurality of input/output geometries (22) positioned about the core cell (14) in which the input/output geometries (22) and cells (20) have no metallization. By depositing metallization, the geometries (22) and cells (20) can be made into input devices or output devices.

Abstract translation: 一种半导体管芯（10），包括用于处理信号的核心单元（14），围绕核心单元（14）定位的多个接合焊盘（18），以及多个未插入接口单元（16），用于输入来自 将所述接合焊盘（18）连接到所述核心单元（14）或将所述信号从所述核心单元（14）输出到所述接合焊盘（18），所述接合焊盘包括位于所述核心单元（14）周围的多个输入/输出几何形状 ），其中输入/输出几何形状（22）和单元（20）没有金属化。 通过沉积金属化，几何形状（22）和单元（20）可以制成输入装置或输出装置。

公开(公告)号：WO1984004009A1

公开(公告)日：1984-10-11

申请号：PCT/US1984000401

申请日：1984-03-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CONSTANTINESCU, Ion

IPC: H03K19/092

CPC classification number: H03K19/01812

Abstract: A new and improved translation circuit (10) that accepts TTL signals and converts them to ECL levels while performing an AND/NAND function is provided, comprising at least two emitter-coupled transistor pairs (Q1-Q2 and Q3-Q4), each coupled to an input terminal (12 and 14) for receiving corresponding TTL signals and coupled to one another for performing the AND operation. Each emitter-coupled pair (Q1-Q2 and Q3-Q4) is also coupled to a bias drive (30) for providing reference voltages that designate which one of each of the transistor pairs (Q1-Q2 and Q3-Q4) conducts, depending upon the state of the TTL signal received.

公开(公告)号：WO1984003587A1

公开(公告)日：1984-09-13

申请号：PCT/US1984000366

申请日：1984-03-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHAN, Hugo, W., K.

IPC: H01L21/74

CPC classification number: H01L29/4933 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76889 ,  H01L23/53271 ,  H01L27/1112 ,  H01L28/20 ,  H01L2924/0002 ,  Y10S257/904 ,  H01L2924/00

Abstract: A fabrication method and result integrated circuit structure that provide a second level of interconnect, a low resistance contact strap (10b) between underlying layers which is not sensitive to alignment and low lateral diffusion polysilicon load. The method comprises the steps of providing contact openings (45a, 45b, 45c) in an insulating layer (40) on a wafer (5) to any desired underlying circuit layers, depositing a silicide layer (50) on the wafer (5), removing selected portions of the silicide layer (50), depositing a polysilicon layer (55) on the wafer (5), lightly doping the polysilicon layer (55) to a level appropriate for the resistor (25), and then removing portions of the polysilicon (55) along with underlying silicide (50).

公开(公告)号：WO1984001471A1

公开(公告)日：1984-04-12

申请号：PCT/US1983001505

申请日：1983-09-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WOLLESEN, Donald, L. ,  SANDER, Craig, S. ,  HASKELL, Jacob, D.

IPC: H01L23/48

CPC classification number: H01L23/53223 ,  H01L21/76889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for integrated circuits having a layer of aluminum (16) and a layer of refractory metal silicide (17) on the aluminum layer (16) to form an aluminum-silicide composite layer. Ranges of suitable thicknesses for the aluminum and metal silicide layers are disclosed. Molybdenum (Mo) and tantalum (Ta) may be used as the refractory metal in the metal silicide layer. Also disclosed is a method of manufacturing an interconnect structure in an integrated circuit providing a first insulating layer (12) over a semiconductor substrate having a plurality of active regions (11) at the surface of the semiconductor substrate (10), forming a first aluminum layer (16) over the first insulating layer (12), forming a metal silicide layer (17) over the aluminum layer (16), and selectively removing parts of the first aluminum layer (16) and the metal silicide layer (17) in a predetermined pattern whereby an aluminum-metal silicide interconnect structure is formed coupling at least some of the active regions (11).

Abstract translation: 一种用于在铝层（16）上具有铝层（16）和难熔金属硅化物层（17）的层的集成电路的互连结构，以形成铝硅化物复合层。 公开了铝和金属硅化物层的合适厚度的范围。 钼（Mo）和钽（Ta）可以用作金属硅化物层中的难熔金属。 还公开了一种在集成电路中制造互连结构的方法，该集成电路在半导体衬底上提供了在半导体衬底（10）的表面上具有多个有源区（11）的半导体衬底上的第一绝缘层（12），形成第一铝 在所述第一绝缘层（12）上形成层（16），在所述铝层（16）上形成金属硅化物层（17），并且选择性地去除所述第一铝层（16）和所述金属硅化物层 形成耦合至少一些有源区（11）的铝 - 金属硅化物互连结构的预定图案。

公开(公告)号：WO1984001066A1

公开(公告)日：1984-03-15

申请号：PCT/US1983001380

申请日：1983-09-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WILSON, Stanley

IPC: H03K19/088

CPC classification number: H03K19/013

Abstract: A transistor logic gate device with a transistor (Q6) coupled between the output terminal (9) and a node of the internal phase splitter subcircuit (4) to speed up switching without requiring an increase in internal current.

公开(公告)号：WO1983002847A1

公开(公告)日：1983-08-18

申请号：PCT/US1982001826

申请日：1982-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  YOUNG, Elvan, S.

IPC: G11C07/00

CPC classification number: G11C29/846

Abstract: Dispositif de mémoire redondante à semiconducteurs permettant de corriger toute colonne défectueuse de cellules binaires dans un réseau de mémoire à semiconducteurs à agencement par bytes. Le dispositif (10) est arrangé en colonnes de cellules binaires (14) adressables par segments de bit (12) avec une pluralité de colonnes séparées et redondantes de cellules binaires, chaque colonne séparée pouvant être placée électroniquement dans toute position de colonne à l'intérieur d'un segment de bit quelconque de la mémoire. D'une manière spécifique, des dispositifs de multiplexage (40) sont prévus sur les tampons de sortie (16) d'une mémoire pour le multiplexage de segments binaires conventionnels avec les colonnes de remplacement de cellules binaires (28 et 30), les colonnes de remplacment étant activées, c'est-à-dire sélectionnées, uniquement lorsqu'une colonne particulière du segment de bit conventionnel a été identifiée comme défectueuse..