公开(公告)号：US20040140467A1

公开(公告)日：2004-07-22

申请号：US10612066

申请日：2003-07-03

Applicant: RENESAS TECHNOLOGY CORP. ,  KYOEI SANGYO CO., LTD.

Inventor： Naoki Kimura ,  Keiji Sugihara

IPC: H01L023/58

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05673 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/05042 ,  H01L2924/19043 ,  H01L2924/00014

Abstract: In a semiconductor device having a pad, a first conductor and a second conductor are arranged at a surface of the pad. The first conductor has hardness that is greater than that of the second conductor and not less than that of a probe stylus. The first conductor is arranged at the surface of the pad such that the probe stylus hits or rubs against the first conductor at least one time while the probe stylus is in contact with and sliding on the surface of the pad.

公开(公告)号：US20040137853A1

公开(公告)日：2004-07-15

申请号：US10742813

申请日：2003-12-23

Applicant: Renesas Technology Corp. ,  TTPCom Limited

Inventor： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC: H04B007/00

CPC classification number: H04B1/30 ,  H03D2200/0047 ,  H03K21/16

Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Abstract translation: 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。

公开(公告)号：US20040137649A1

公开(公告)日：2004-07-15

申请号：US10437911

申请日：2003-05-15

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takeshi Kishida ,  Shigenori Kido

IPC: H01L021/00

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A photolithography step is carried out for exposing/etching a resist film in an etching step. Thereafter a superposition inspection step employing a superposed layer superposition mark and a resist film superposition mark is carried out with a superposition inspection apparatus. In this step, an applied mask confirmation step is simultaneously carried out with the superposition inspection apparatus. Thus, it is possible to provide a method of fabricating a semiconductor device including a superposition inspection step, capable of efficiently confirming an applied mask and improving the fabrication yield for the semiconductor device.

Abstract translation: 在蚀刻步骤中进行曝光/蚀刻抗蚀剂膜的光刻步骤。 此后，使用重叠检查装置进行使用叠加层叠加标记和抗蚀剂膜叠加标记的叠加检查步骤。 在该步骤中，与叠加检查装置同时进行应用的掩模确认步骤。 因此，可以提供一种制造包括叠加检查步骤的半导体器件的方法，其能够有效地确认所施加的掩模并且提高半导体器件的制造成品率。

公开(公告)号：US20040124506A1

公开(公告)日：2004-07-01

申请号：US10729950

申请日：2003-12-09

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd. ,  Renesas Eastern Japan Semiconductor, Inc.

Inventor： Fujio Ito ,  Hiromichi Suzuki ,  Hiroyuki Takeno ,  Hiroshi Shimoji ,  Fumio Murakami ,  Keiko Kurakawa

IPC: H01L023/495

CPC classification number: H01L24/97 ,  H01L21/565 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract translation: 旨在提高QFN（四方扁平无铅封装）的生产成本，达到多引脚结构。 在通过模塑形成用于密封半导体芯片的树脂密封构件之后，树脂密封构件的周边部分和引线框架都沿着位于树脂密封构件的内侧（树脂密封构件的中心侧）上的切割线切割 沿着树脂密封构件的外缘延伸的线（成型线），从而覆盖暴露于树脂密封构件的侧面（切割面）的各个引线的整个表面（上下表面和两个侧面） 树脂，从而防止在引线的切割面上发生金属毛刺。

公开(公告)号：US20040120195A1

公开(公告)日：2004-06-24

申请号：US10725477

申请日：2003-12-03

Applicant: Renesas Technology Corp.

Inventor： Yuichi Okuda

IPC: G11C029/00

CPC classification number: H01L23/576 ,  G06K19/073 ,  G06K19/07372 ,  G11C11/412 ,  G11C11/4125 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously. Reverse engineering by irradiation with light can be effectively prevented.

Abstract translation: 提供一种能够防止卡黑入侵的半导体集成电路，由此通过照射光和被保护的秘密信息主动地引起错误的动作被非法获取。 由标准逻辑处理配置的光检测器安装在诸如IC卡微计算机的半导体集成电路上，与其他电路几乎不区分并且消耗非常少的待机功率。 例如，每个光电检测器具有这样的配置，其中第一状态通过其初始化动作保持在静态锁存器中，并且当非导通状态的半导体元件构成静态锁存器时，发生反向到第二状态 第一个状态被光照射。 多个光电检测器被布置在存储单元阵列中。 通过将静态锁存型光电检测器结合到存储器阵列中，它们可以不显眼地排列。 可以有效地防止用光照射进行逆向工程。

公开(公告)号：US20040119723A1

公开(公告)日：2004-06-24

申请号：US10454506

申请日：2003-06-05

Applicant: Renesas Technology Corp.

Inventor： Yoshitsugu Inoue ,  Akira Torii

IPC: G09G005/00

CPC classification number: G06T11/60 ,  G06T15/10

Abstract: An apparatus for manipulating a face image such as a portrait which produces visual effects to keep interesting a user with simple processes without requiring preparation of a complex model and a number-crunching process for processing the model is provided. Boundary determining means (111) determines a boundary used for bending a face image in a vertical direction of a face image. Image manipulating means (116) bends the face image based on the boundary as determined, to make the face image convex or concave locally around the boundary. Thereafter, the image manipulating means (116) rotates the face image about a rotation axis defined so as to extend in a horizontal direction of the face image, and thereafter projects the face image onto a plane. With those procedures, an expression of a face of the face image can be varied.

Abstract translation: 提供了一种用于操纵诸如肖像的面部图像的装置，其产生视觉效果以使用户简单的过程而不需要准备复杂的模型和用于处理该模型的数字处理过程。 边界确定装置（111）确定用于在面部图像的垂直方向上弯曲脸部图像的边界。 图像处理装置（116）基于所确定的边界弯曲面部图像，以使面部图像在边界周围局部地凸起或凹入。 此后，图像处理装置（116）围绕围绕面部图像的水平方向限定的旋转轴旋转面部图像，然后将面部图像投影到平面上。 通过这些程序，可以改变脸部图像的脸部表情。

公开(公告)号：US20040113904A1

公开(公告)日：2004-06-17

申请号：US10716459

申请日：2003-11-20

Applicant: Renesas Technology Corp.

Inventor： Atsushi Nakamura ,  Kenichiro Omura

IPC: G09G005/00

CPC classification number: G09G5/363 ,  G09G5/397 ,  G09G2320/0247 ,  G09G2340/02

Abstract: Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a display system, versatile switching between image data storage areas is enabled without heavily loading a central processing unit. Attribute bits of a TRAP command indicating the termination of drawing of one display plane are provided with display switching enable bits indicating whether to perform switching between image data storage areas for each display plane. For display planes corresponding to the display switching enable bits of null1null, switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.

Abstract translation: 为能够叠加显示的多个显示平面中的每一个分配多页的图像数据存储区域，并且在为每个显示平面执行图像数据存储区域之间切换的同时执行显示输出处理。 在这种显示系统中，能够在不大量加载中央处理单元的情况下启用图像数据存储区域之间的通用切换。 指示终止一个显示平面的TRAP命令的属性位被提供有指示是否在每个显示平面的图像数据存储区域之间进行切换的显示切换使能位。 对于与“1”的显示切换使能位相对应的显示平面，切换到与下一个垂直同步信号同步的定时从其读取图像数据的图像数据存储区域。

公开(公告)号：US20040111592A1

公开(公告)日：2004-06-10

申请号：US10445831

申请日：2003-05-28

Applicant: Renesas Technology Corp.

Inventor： Chuma Nagao ,  Hiroshi Ueki

IPC: G06F009/44

CPC classification number: G06F9/3804 ,  G06F9/3842 ,  G06F9/3885

Abstract: A microprocessor is provided with two queue buffers, one for storing prefetched non branch instructions and the other for storing prefetched branch target instructions, and a plurality of process stages. The process stages are divided into one last process stage and other process stages those form two different paths. Non branch instructions are processed in one path and branch target instructions are processed in other path. The paths are changed based on whether branch condition is met or not.

Abstract translation: 微处理器具有两个队列缓冲器，一个用于存储预取的非分支指令，另一个用于存储预取的分支目标指令，以及多个处理阶段。 过程阶段分为最后一个过程阶段和其他形成两个不同路径的过程阶段。 非分支指令在一个路径中处理，分支目标指令在其他路径中处理。 路径根据是否满足分支条件而改变。

公开(公告)号：US20040108559A1

公开(公告)日：2004-06-10

申请号：US10673789

申请日：2003-09-30

Applicant: Renesas Technology Corp.

Inventor： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

IPC: H01L029/76

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/802

Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

Abstract translation: 利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。 此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。 根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。

公开(公告)号：US20040108534A1

公开(公告)日：2004-06-10

申请号：US10455325

申请日：2003-06-06

Applicant: Renesas Technology Corp.

Inventor： Takaaki Tsunomura ,  Masahiko Takeuchi

IPC: H01L027/108

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

Abstract: A storage node in a capacitor of a semiconductor device is formed of: an inner conductor in a columnar form having bottom, side and top surfaces; and an outer conductor, located on the bottom (between the bottom surface and the semiconductor substrate), side and top surfaces of the inner conductor, having a different material from that of the inner conductor. The outer conductor is formed of a metal film such as of Ru having a film thickness of about 40 nm to 80 nm. The inner conductor is formed of a film, such as a TiN film, a TaN film, a WN film or the like, having a high adhesion to the metal film such as of Ru. With this configuration, it is possible to provide a semiconductor device provided with a capacitor of which the capacitance is obtained.

Abstract translation: 半导体器件的电容器中的存储节点由具有底部，侧面和顶部表面的柱状形式的内部导体形成; 以及位于底部（底面和半导体衬底之间），内部导体的侧表面和顶表面之间的外部导体，其具有与内部导体不同的材料。 外导体由膜厚为约40nm至80nm的诸如Ru的金属膜形成。 内部导体由诸如RuN的金属膜具有高粘附性的诸如TiN膜，TaN膜，WN膜等的膜形成。 利用这种配置，可以提供一种设置有获得电容的电容器的半导体器件。