公开(公告)号：JP2002112980A

公开(公告)日：2002-04-16

申请号：JP2001257286

申请日：2001-08-28

Applicant: ST MICROELECTRONICS INC

Inventor： GOZZINI GIOVANNI

IPC: A61B5/117 ,  G06K9/00 ,  G06T1/00

Abstract: PROBLEM TO BE SOLVED: To provide a technique that improves safety in fingerprint detection. SOLUTION: In a capacitive fingerprint detector, fingers are detected by a capacitive grid positioned in the upper side of a fingerprint sensor electrode for measuring the absolute capacitance of the fingers arranged on the surface of the sensor. The capacitance measurement is converted into a representative frequency, and subsequently compared with a reference frequency or frequency range and it is determined whether the capacitance measured agrees with predicted biological characteristics of live skin tissue. Therefore, this fingerprint detection protects against a cheat in a fingerprint detector.

公开(公告)号：JP2002095277A

公开(公告)日：2002-03-29

申请号：JP2001224590

申请日：2001-07-25

Applicant: ST MICROELECTRONICS INC

Inventor： MENEGOLI PAOLO ,  ENDEL TSUNKU EROGURU ,  WITNEY FUI RI

IPC: G05D3/12 ,  G11B19/28 ,  H02P29/00 ,  H02P5/00

Abstract: PROBLEM TO BE SOLVED: To provide a disk drive capable of dynamically correcting and shortening a processing time. SOLUTION: The disk drive comprises a motor and a speed control loop. The speed control loop has a frequency sensor and a filter. The filter has a filter section and an accumulator. The filter is programmable in such function as dynamically receiving a filter coefficient by the filter section.

公开(公告)号：JP2001357695A

公开(公告)日：2001-12-26

申请号：JP2001130761

申请日：2001-04-27

Applicant: ST MICROELECTRONICS INC

Inventor： WORLEY JAMES L

IPC: G11C11/401 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM device having twist type bit line architecture in which a redundant row consisting of memory cells can be effectively used when a memory cell row has a defect. SOLUTION: A form of a pair of redundant row can be specified to replace any one of rows consisting of memory cells having defect in a redundant row decoding circuit. Each pair of bit line is integrated to a separate memory cell from each redundant row of pairs of redundant row, therefore, both of true version and complement version of a data value are kept by the pair of redundant row. A row consisting of reference cells is cut off and/or disabled during a memory access operation period related by the pair of redundant row.

公开(公告)号：JP2001297534A

公开(公告)日：2001-10-26

申请号：JP2001036767

申请日：2001-02-14

Applicant: ST MICROELECTRONICS INC

Inventor： OZDEMIR HAKAN

IPC: G11B5/012 ,  G11B20/10 ,  H03G3/20 ,  H03M1/18

Abstract: PROBLEM TO BE SOLVED: To provide a circuit and method for controlling the gain of an amplifier in accordance with the sum of the samples of amplified signals and a technique of increasing memory density by shortening the preambles recorded on a recording medium. SOLUTION: This circuit controls the gain of the amplifier which amplifies information signals. The circuit has a buffer for storing the first and second samples of the amplified information signals and a gain determining circuit coupled to these buffers. The gain determining circuit generates gain adjustment in accordance with the sum of the first and second samples. The gain adjustment changes the amplification of the information signals amplified by the amplifier to the prescribed amplification or toward the same. Such circuit can impart the initial rough gain adjustment to the reading signal amplifier in a disk drive reading channel. As compared to the conventional reading channel, this initial adjustment promotes the stabilization faster than the gain of the amplifier in the beginning of data sectors. The faster stabilization enables the data sectors to have the shorter preambles and consequently the disk can have the higher data storage (memory) density.

公开(公告)号：JP2001291341A

公开(公告)日：2001-10-19

申请号：JP2001036455

申请日：2001-02-14

Applicant: ST MICROELECTRONICS INC

Inventor： OZDEMIR HAKAN

IPC: G11B20/10 ,  G11B20/14 ,  H03L7/091

Abstract: PROBLEM TO BE SOLVED: To increase the memory capacity of a recording medium by shortening the preamble to be recorded on the recording medium. SOLUTION: A phase calculation circuit has a buffer, an approximation circuit and an interpolator. The buffer receives and stores the first and second samples of periodic signals having peak amplitude. This approximation circuit linearly approximates part of the periodic signals and calculates one relative phase among the samples within the signal segments. The interpolator calculates the relative phase of one sample relating to the prescribed point of the signals by using the values of the relative phase and first and second samples of the samples within the signal segments. Such circuit may be used to decrease the matching acquisition time of a digital timing restoration loop and is therefore capable of shortening the perample and increasing the data memory density of a disk.

公开(公告)号：JP2001223698A

公开(公告)日：2001-08-17

申请号：JP2000382220

申请日：2000-12-15

Applicant: ST MICROELECTRONICS INC

Inventor： FUNG ANTHONY ,  PETER GROSS ,  HUI DANNY ,  HVOSTOV HARRY ,  SABY BERNARD

IPC: G06F13/00 ,  H04L12/24 ,  H04L12/28 ,  H04L12/26

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method that specify and manage a mode of connection of a broadband cable modem network station to a network. SOLUTION: This system has a state drive type network manager that has functions such as a central error processing state, initialization, dynamic host configuration, configuration download, start simple network management and peripheral state to an operating state. In the operating state, an error and other messages communicated from the other state are monitored, an error message is set to the central type error processing state, and a message is requested to an operation support system interface management task. The error processing state receives the error message and requests an error event logging from an operation support system interface management task. A revision upper-stream or downstream channel task optimizes channel selection.

公开(公告)号：JP2001211230A

公开(公告)日：2001-08-03

申请号：JP2000378603

申请日：2000-12-13

Applicant: ST MICROELECTRONICS INC

Inventor： SABY BERNARD ,  HVOSTOV HARRY ,  FUNG ANTHONY

IPC: H04L29/10 ,  H04L12/28 ,  H04L12/40

Abstract: PROBLEM TO BE SOLVED: To provide an enhanced cable modem link layer bridge. SOLUTION: The cable modem link layer bridge includes a downstream transfer task and an upstream transfer task. The downstream transfer task is configured to receive a 1st message from a cable network and transfer the 1st message to equipment (CPE) at customer's premises. The upstream transfer task is configured to receive a 2nd message from the CPE and transfer the 2nd message to the cable network, and multi-task processing is applied to the upstream transfer task and the downstream transfer task so that the upstream transfer task transfers the 2nd message, while the downstream transfer task transfers the 1st message.

公开(公告)号：JP2001156653A

公开(公告)日：2001-06-08

申请号：JP2000298432

申请日：2000-09-29

Applicant: ST MICROELECTRONICS INC

Inventor： REZZI FRANCESCO ,  MARROW MARCUS

IPC: G11B20/10 ,  G11B20/18 ,  H03M13/41

Abstract: PROBLEM TO BE SOLVED: To provide an enhanced technology to recover information from a read signal. SOLUTION: The Viterbi detector of this invention receives a signal representing a sequence consisting of a plurality of values. The detector identifies a survivor path from a possible sequence value and periodically eliminates the identified survivor path with a prescribed parity to recover the sequence from the signal. The Viterbi detector as above can accurately recover data from a read signal with a deteriorated SNR by recognizing the parity being part of a data sequence and can increase a storage density of a storage disk of a disk drive.

公开(公告)号：JP2001118937A

公开(公告)日：2001-04-27

申请号：JP2000275326

申请日：2000-09-11

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU CHIU ,  ZAMANIAN MEHDI

IPC: H01L21/8244 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which is usable in severe radiating environments, such as in outer space. SOLUTION: The device includes an active gate-isolating structure, which is disposed in series with an oxide isolating region between active regions of a memory cell array. The active gate-isolating structure has a polysilicon gate layer coupled electrically to a gate oxide and a supply terminal, and the active gate isolating structure prevents an adjacent active region from extending to form a conducting channel. The gate oxide of the active gate isolating structure is relatively thinner than that of a conventional oxide isolating region. Consequently, adverse effects of electric charges captured by radiation can be reduced.

公开(公告)号：JP2001093987A

公开(公告)日：2001-04-06

申请号：JP2000230590

申请日：2000-07-31

Applicant: ST MICROELECTRONICS INC

Inventor： GAO GUANG-BO ,  HOANG HOANG HUY

IPC: H01L21/762 ,  H01L21/316 ,  H01L21/76 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/092 ,  H01L29/38 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To improve the speed of a semiconductor integrated circuit utilizing the electrical characteristics of a different substance. SOLUTION: By utilizing high electron mobility for GeAs in an N-channel device and a high hole mobility for Ge in a P-channel device, a CMOS integrated circuit with GaAs/Ge is formed on an Si for improving the switching (propagation) delay of a transistor. A semi-insulation (non-doped) layer 102b of GaAs is formed on a silicon base 102a for giving a buffer layer, thus eliminating the possibility of latch-up. Then, a GaAs well 106 and a Ge well 110 are formed on the semi-insulation GaAs layer 102b for electrical isolation by thermal oxide and/or flowing oxide (HSQ) 112. By forming an N-channel MOS device 114 and a P-channel MOS device 116 in the GaAs well 106 and the Ge well 110, respectively, an integrated circuit is formed by interconnection.