公开(公告)号：EP1445889A1

公开(公告)日：2004-08-11

申请号：EP03250714.7

申请日：2003-02-04

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew

IPC: H04L9/00

CPC classification number: H04L9/0631 ,  H04L9/0827 ,  H04L2209/601

Abstract: A semiconductor integrated circuit (39) comprising: a plurality of selectable pathways (23) inter-connected between a plurality of data sources and data destinations (11, 13, 15, 17, 19); a cryptographic circuit (9) connected to the selectable pathways (23) and arranged to selectively receive data at an input (24) from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and selectively provide the encrypted or decrypted data to at least one of the data destinations via an output (26); an instruction interpreter (29) arranged to receive as an input an instruction signal (33) and to generate therefrom an output (31) to control the plurality of selectable pathways (23) to select from which of the data sources the cryptographic circuit (9) receives data and to which destination the cryptographic circuit (9) provides data; the instruction interpreter (29) being configured such that the instruction signal (33) defines a data pathway configuration of the system, and such that it operates in accordance with a rule which limits the data pathway configurations which are selectable. Preferably, the instruction interpreter (29), cryptographic circuit (9) and data pathways (23) are all contained on a single monolithic semiconductor integrated circuit (39).

Abstract translation: 一种半导体集成电路（39），包括：多个可选路径（23），其彼此连接在多个数据源和数据目的地（11,13,15,17,19）之间; 连接到所述可选择路径（23）并被布置成在至少一个所述数据源的输入端（24）选择性地接收数据的密码电路（9），以便根据密钥对所述数据进行解密或加密，并选择性地提供 经由输出（26）将加密或解密的数据传送到至少一个数据目的地; 指令解释器（29），布置成作为输入接收指令信号（33），并从其中产生输出（31），以控制多个可选路径（23），从多个数据源中选择加密电路（9） ）接收数据，加密电路（9）提供数据到哪个目的地; 所述指令解释器（29）被配置为使得所述指令信号（33）定义所述系统的数据通路配置，并且使得所述指令信号（33）根据限制可选择的数据通路配置的规则进行操作。 优选地，指令解释器（29），密码电路（9）和数据通路（23）都包含在单个单片半导体集成电路（39）上。

公开(公告)号：EP1429470A2

公开(公告)日：2004-06-16

申请号：EP03028714.8

申请日：2003-12-12

Applicant: STMicroelectronics Limited

Inventor： Stopler, Danny

IPC: H04B3/23

CPC classification number: H04B3/23 ,  H04M9/082

Abstract: A receiver (20) for receiving an incoming signal over a communication medium includes an echo canceller (44), which is adapted to receive an outgoing signal transmitted over the communication medium, and to process the outgoing signal using a set of variable processing coefficients in order to generate an echo cancellation signal. A summer (46) combines the incoming signal with the echo cancellation signal so as to generate an echo-cancelled signal. An equalizer (48) applies an equalization operation to the echo-cancelled signal so as to generate an equalized signal. A residual echo cancellation circuit (58) processes the equalized signal so as to adaptively update the variable processing coefficients of the echo canceller.

Abstract translation: 用于通过通信介质接收输入信号的接收机（20）包括回波消除器（44），其适于接收通过通信介质发送的输出信号，并使用一组可变处理系数来处理输出信号 以产生回声消除信号。 夏季（46）将输入信号与回波消除信号相结合，以产生回声消除信号。 均衡器（48）对回声消除信号施加均衡操作，以产生均衡信号。 残余回声消除电路（58）处理均衡信号，以自适应地更新回波消除器的可变处理系数。

公开(公告)号：EP1388775A1

公开(公告)日：2004-02-11

申请号：EP02255482.8

申请日：2002-08-06

Applicant: STMicroelectronics Limited

Inventor： Rashid, Tahir

IPC: G05F3/22

CPC classification number: G05F3/225 ,  G05F3/30

Abstract: The invention relates to a voltage reference generator which can be produced using new process technologies and which is still compatible with older designs/products. This is achieved by the introduction of circuitry to generate an offset voltage independently of the main reference voltage generation circuitry.

Abstract translation: 本发明涉及一种电压参考发生器，其可以使用新的工艺技术制造，并且仍然与旧的设计/产品兼容。 这通过引入电路来实现，以产生独立于主参考电压产生电路的偏移电压。

公开(公告)号：EP1321984A3

公开(公告)日：2004-01-14

申请号：EP01307231.9

申请日：2001-08-24

Applicant: STMicroelectronics Limited

Inventor： Thies, William ,  Froidevaux, Nicolas

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/06153

Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

公开(公告)号：EP0702243B1

公开(公告)日：2004-01-07

申请号：EP95305863.3

申请日：1995-08-22

Applicant: STMicroelectronics Limited

Inventor： Felix, Stephen

IPC: G01R31/3185 ,  G06F11/267 ,  H03K3/037

CPC classification number: H03K3/0375 ,  G01R31/30 ,  G01R31/318541

公开(公告)号：EP1353440A1

公开(公告)日：2003-10-15

申请号：EP02252623.0

申请日：2002-04-12

Applicant: STMicroelectronics Limited

Inventor： Darzy, Saul

IPC: H03F3/30

CPC classification number: H03F3/3067

Abstract: This invention relates to a circuit used in the output stage of an operational amplifier which allows a rail to rail swing of the output voltage while consuming low quiescent power. The circuit comprising first (Q1) and second (Q2) control elements each having a controllable path and a control node. The circuit further comprises a third control element (Q3) having a controllable path connected between said control nodes of said first and second control elements via a resisted path (R1,R2). A voltage indicative of a signal input to amplifier is received by a node on the resistive path (R1,R2), such that current flow through the controllable path of said first control element (Q1) and said third element (Q3) changes in response to a change in the voltage at said node; and such that current flow through said controllable path of said second element (Q2) changes independence on the current flow through the controllable path of said third control elements (Q3), whereby as one of the first and second control elements (Q1,Q2) is turned on, the other is held off.

Abstract translation: 本发明涉及在运算放大器的输出级，其允许轨与输出电压的轨摆动，同时消耗低静态功率使用的电路。 该电路包括第一开关（Q1）和第二（Q2）的控制元件的每个具有可控路径和控制节点。 该电路还包括具有通过抵制路径（R1，R2），其连接所述第一和第二控制元件的所述控制节点之间的可控路径的第三控制元件（Q3）。 表示输入到放大器的信号的电压通过电阻路径（R1，R2）上的一个节点接收到的，检测通过所述第一控制元件（Q1）的所述可控路径没有电流流动，并且所述响应第三元件（Q3）的变化 以在节点。所述的电压变化; 并且这样做通过的所述第二元件（Q2）的变化对电流流过所述第三控制元件（Q3）的可控路径，独立所述可控路径的电流流动，由此作为第一和第二控制元件中的一个（Q1，Q2） 开启时，另一种是挡住。

公开(公告)号：EP1345177A1

公开(公告)日：2003-09-17

申请号：EP02251703.1

申请日：2002-03-11

Applicant: STMicroelectronics Limited

Inventor： Brkic, Toni

IPC: G06T11/40 ,  G06T11/00

CPC classification number: G06T11/40

Abstract: Method and computer graphics accelerator apparatus for determining whether a pixel at predetermined pixel co-ordinates in an area being rasterised is within a triangle defining a sub-area of the area. The system in relation to which the triangle is defined is translated such that the pixel co-ordinates are disposed at the origin of the system. Determinants of matrices based on at least two of the coordinate values of at least two of the vertices are calculated and their signs compared.

Abstract translation: 无论是在预定的像素坐标在区域中的像素被光栅化用于计算机图形加速器确定性采矿方法和装置的区域的三角形限定的子区域内。 关于该系统到的三角形被定义平移检查做的像素坐标是在该系统的原点处。矩阵的行列式的基于至少两个的至少两个顶点的坐标值的计算和 自己的招牌相比。

公开(公告)号：EP1335587A1

公开(公告)日：2003-08-13

申请号：EP02425061.5

申请日：2002-02-08

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Limited

Inventor： Findlater, Keith ,  Henderson, Robert ,  Smith, Stewart ,  Hurwitz, Jonathan ,  Guarnera, Mirko

IPC: H04N3/15

CPC classification number: H04N5/374 ,  H04N5/3456 ,  H04N5/3458 ,  H04N9/045

Abstract: A digital camera for capturing and processing images of different resolutions is described together with a method for down-scaling a digital image. The method comprises the steps of forming an image of a real scene on an image sensor (4) comprising a plurality of pixels arranged in a matrix, addressing and reading pixels in the matrix to obtain analogue quantities related with the pixels luminance values, converting (5) the analogue quantities from the pixels matrix into digital values and processing (6-13) the digital values to obtain a data file representing the image of the real scene. To reduce computation time and power consumption the step of addressing and reading pixels includes the steps of selecting a group of pixels from the matrix, storing the analogue quantities related with the pixels of the selected group of pixels into analogue storing means (14) and averaging the stored analogue quantities to obtain an analogue quantity corresponding to an average pixel luminance value.

Abstract translation: 用于捕获和处理不同分辨率的图像的数字照相机与用于比例缩小的数字图像的方法一起描述。 该方法包括在（图像传感器（4），包括以矩阵排列的像素的复数，寻址和在基体中，以获得与所述像素的亮度值相关的类似物的量读出诸像素形成真实场景的图像的步骤，转换 5）来自像素的模拟量矩阵成数字值和处理（6-13）的数字值，以获得表示所述真实场景的图像的数据文件。 为了减少计算时间和功耗寻址和读出的像素的步骤包括选择一组像素的从矩阵，存储与像素的选择的组的像素的相关成模拟存储装置（14）和平均模拟量的步骤 所存储的模拟量，以获得对模拟量对应于平均像素亮度值。

公开(公告)号：EP0942371B1

公开(公告)日：2003-05-21

申请号：EP99301834.0

申请日：1999-03-11

Applicant: STMicroelectronics Limited

Inventor： Edwards, David Alan ,  Jones, Andrew Michael

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/3648

公开(公告)号：EP1304619A1

公开(公告)日：2003-04-23

申请号：EP01308961.0

申请日：2001-10-22

Applicant: STMicroelectronics Limited

Inventor： Southwell, Trefor ,  Hedinger, Peter

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.

Abstract translation: 高速缓存存储器包括：提取引擎，被配置为发出取出请求，用于从正在执行的程序中的访问地址识别的主存储器中的位置访问数据项，控制该预取引擎发出预取请求以推测访问预取 来自所述主存储器中的位置的数据项由被确定为来自所述访问地址的相应位置的位置数的地址所标识;以及校准器，被配置为选择性地改变所述位置数。