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公开(公告)号：US20230171951A1
公开(公告)日：2023-06-01
申请号：US17809667
申请日：2022-06-29
Inventor： Guangsu SHAO , Deyuan XIAO , Yunsong QIU , Mengkang YU
IPC: H01L27/108
CPC classification number: H01L27/10823 , H01L27/10876
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes a plurality of active pillars, a dielectric layer that is disposed around a circumference of the active pillar and that covers a part of a sidewall of the active pillar, and a word line. Any two adjacent ones of the plurality of active pillars are separated by using a first trench or a second trench. The first trench and the second trench are staggered. The second trench is wider than the first trench. The dielectric layer is disposed around the circumference of the active pillars. The word line partially covers the dielectric layer, and fills a part of the first trench located between adjacent active pillars.
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公开(公告)号：US20230170382A1
公开(公告)日：2023-06-01
申请号：US18054980
申请日：2022-11-14
Inventor： Mengkang YU , Xingsong Su , Weiping Bai
IPC: H01L29/94
Abstract: The present disclosure provides a capacitor and a manufacturing method thereof, and a semiconductor device. The capacitor includes a plurality of bottom electrodes, a top electrode structure, a dielectric layer, and a gap filling layer, where the top electrode structure is formed on one side of each of the plurality of bottom electrodes, one side of the dielectric layer is in contact with the plurality of bottom electrodes and the other side is in contact with the top electrode structure, and the gap filling layer fills remaining gaps between the plurality of bottom electrodes.
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公开(公告)号：US20230066016A1
公开(公告)日：2023-03-02
申请号：US17808372
申请日：2022-06-23
Inventor： Xiaoguang WANG , Dinggui ZENG , Huihui LI , Kanyu CAO
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a plurality of memory cells alternately arranged on a substrate, the memory cell including an odd number of vertical transistors, a connection pad connected to one end of each of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad; wherein a material of a channel of the vertical transistor includes a monocrystalline semiconductor.
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公开(公告)号：US20230064521A1
公开(公告)日：2023-03-02
申请号：US17828462
申请日：2022-05-31
Inventor： Guangsu Shao , Deyuan Xiao , Qinghua Han , Yunsong Qiu , Weiping Bai
IPC: H01L27/108 , H01L29/786 , H01L29/66
Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method for forming the semiconductor structure includes the following operations. A base is provided, in which the base includes a substrate, a first semiconductor layer and a second semiconductor layer sequentially formed on one another. A plurality of first isolation structures spaced apart from each other and a plurality of second isolation structures spaced apart from each other are formed in the base. A channel layer is formed in the first semiconductor layer, in which a through hole is provided between the channel layer and each of two first isolation structures adjacent to the channel layer. A gate structure is formed in the through hole.
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公开(公告)号：US20230061246A1
公开(公告)日：2023-03-02
申请号：US17857219
申请日：2022-07-05
Inventor： Xiaoguang WANG , Dinggui ZENG , Huihui LI , Kanyu CAO
Abstract: A semiconductor structure, a manufacturing method therefor and a memory are provided. The semiconductor structure may at least include: a plurality of aligned transistors, in which the transistors share a same source plate, channels of the transistors are located above the source plate, the channel length direction of the transistors is perpendicular to a surface of the source plate, and a material of the channels includes a single crystal semiconductor; a plurality of drain contacts, electrically connected with drains of the transistors, in which even number of the transistors share one same drain contact; and a plurality of magnetic tunnel junctions, located on the drain contacts and electrically connected with the drain contacts in one-to-one correspondence.
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Patent Agency Ranking
公开(公告)号：US20230015279A1
公开(公告)日：2023-01-19
申请号：US17952383
申请日：2022-09-26
Inventor： Guangsu SHAO , Deyuan XIAO , Weiping BAI
IPC: H01L27/108 , G11C5/06
Abstract: A method for forming a semiconductor device includes the following operations. A stacked structure is provided, which includes a substrate, and sacrificial layers and semiconductor layers alternately stacked on surface of the substrate. Multiple first grooves and semiconductor pillars extending in first direction are included in the sacrificial layers and the semiconductor layers. Word line pillars are formed in second direction, intersect with the semiconductor pillars and surround the semiconductor pillars. Sources and drains are formed respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process. Bit lines are formed on a side of the sources or the drains, are connected with same, and extend in third direction. The first, second and third directions are pairwise perpendicular. Capacitors are formed on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.
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公开(公告)号：EP4394772A1
公开(公告)日：2024-07-03
申请号：EP22934532.7
申请日：2022-06-08
Inventor： ZHU, Zhengyong , KANG, Bokmoon , WANG, Guilei , ZHAO, Chao
IPC: G11C11/407
Abstract: Embodiments of the present invention provide a memory and a manufacturing method therefor, and an electronic device. The memory comprises a substrate, and a word line, a bit line and a storage unit on one side of the substrate. The storage unit comprises a transistor. The transistor comprises: a semiconductor layer which comprises a source contact region, a semiconductor region, and a drain contact region which are sequentially connected; a main gate electrically connected to the word line; a source electrically connected to the bit line and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain. The orthographic projection of the main gate on the substrate and the orthographic projection of the secondary gate on the substrate at least partially overlap with the orthographic projection of the semiconductor region of the semiconductor layer on the substrate. According to the present invention, on the basis that the transistor has the main gate, the secondary gate electrically connected to the drain is introduced, the secondary gate can obtain a fixed potential synchronous with the drain, and provide supplement control for the semiconductor layer by utilizing the fixed potential, thereby optimizing the read-write performance of the memory.
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公开(公告)号：EP4380330A1
公开(公告)日：2024-06-05
申请号：EP22955194.0
申请日：2022-12-07
Inventor： DAI, Jin , YU, Yong , LIANG, Jing
IPC: H10B12/00
Abstract: The present disclosure provides a memory cell, a 3D memory and a preparation thereof, and an electronic device, and relates to the technical field of semiconductor technology. The memory cell includes a first transistor and a second transistor disposed on a substrate (1), the first transistor includes a first gate (11), a first electrode (33), a second electrode (34) and a first semiconductor layer (6) disposed on the substrate; the second transistor includes a third electrode (51) , a fourth electrode (52), a second gate (12) extending in a direction perpendicular to the substrate (1) and a second semiconductor layer (9) surrounding a sidewall of the second gate (12) which are disposed on the substrate (1), the second semiconductor layer (9) includes a second source contact region (91) and a second drain contact region (92) arranged at intervals, a channel between the second source contact region (91) and the second drain contact region (92) is a horizontal channel.
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公开(公告)号：EP4167276A1
公开(公告)日：2023-04-19
申请号：EP22732384.7
申请日：2022-02-25
Inventor： Shao, Guangsu , Bai, Weiping , Xiao, Deyuan , Qiu, Yunsong
IPC: H01L21/8242 , H01L27/108
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and solves the technical problem of a high parasitic capacitance of the semiconductor structure. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps. By forming the air gaps, and exposing parts of the side surfaces of the BLs in the air gaps, the present disclosure reduces the dielectric constant of the structure between the BLs and the parasitic capacitance of the semiconductor structure.
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公开(公告)号：EP4380329A1
公开(公告)日：2024-06-05
申请号：EP22955193.2
申请日：2022-12-07
Inventor： DAI, Jin , YU, Yong , LIANG, Jing
IPC: H10B12/00 , H01L29/786
Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate (1), and a word line (110). A memory cell includes a transistor which includes a source (51) and a drain (52), a gate (11) extending in the direction perpendicular to the substrate (1), a semiconductor layer (9) surrounding a sidewall of the gate (11). The semiconductor layer (9) includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line (110) extends in the direction perpendicular to the substrate (1) and penetrates through the memory cells of different layers.
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