公开(公告)号：JP2003152119A

公开(公告)日：2003-05-23

申请号：JP2002252983

申请日：2002-08-30

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide an FAMOS memory location which can have at least three completely natural program levels. SOLUTION: An FAMOS memory location is provided with a single floating gate (GR) overlapping the active plane of a semiconductor substrate along contour (PF1, PF2) of at least two asymmetric overlaps in order to determine at least two electrodes in an active region. A memory location program means (MC, SW) applies a set of specified different voltages selectively to the electrodes such that at least three program logical levels are outputted to the memory location.

公开(公告)号：JP2003031611A

公开(公告)日：2003-01-31

申请号：JP2002142521

申请日：2002-05-17

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： VARROT MICHEL ,  BOUCHE GUILLAUME ,  GONELLA ROBERTO ,  SABOURET ERIC

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48475 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/85051 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  Y10S257/92 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: PROBLEM TO BE SOLVED: To provide the configuration of a connecting pad to minimize and remove the risk of peeling of a layer and a fine crack. SOLUTION: The integrated circuit comprises a plurality of metallization levels and connecting pads. Each connecting pad PLC is allocated in the highest metallization level. On the upper surface of the connecting pad, a metal layer CMS of the highest metallization level including an area for welding a connecting wire, at least one noncontinuous metal layer CMD4 in the lowest metallization level next to the above layer, a metal via VS connecting the non-continuous metal layer at the lower surface of the metal layer in the highest metallization level, and an insulation cover OX covering the non-continuous metal layer and the non-continuous part in addition to the inter-via between two metal layers, are respectively provided. Moreover, a reinforcing configuration STR is also included under a coupled region.

Abstract translation: 要解决的问题：提供连接垫的结构，以最小化并消除层剥离和细裂纹的风险。 解决方案：集成电路包括多个金属化层和连接焊盘。 每个连接焊盘PLC分配在最高的金属化级别。 在连接焊盘的上表面上，包括用于焊接连接线的区域的最高金属化水平的金属层CMS，与上述层相邻的最低金属化水平中的至少一个非连续金属层CMD4，金属通孔VS连接 在最高金属化水平的金属层的下表面处的非连续金属层和除了两个金属层之间的通孔之外覆盖非连续金属层和非连续部分的绝缘盖OX， 分别提供。 此外，加强配置STR也包括在耦合区域下。

公开(公告)号：JP2002305110A

公开(公告)日：2002-10-18

申请号：JP2002032034

申请日：2002-02-08

Applicant: ST MICROELECTRONICS SA

Inventor： LEMAIRE FREDERIC

IPC: H01F17/00 ,  H01F17/02 ,  H01F27/36 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a new integrated circuit inductance structure which can overcome the problems which are known in inductance structure. SOLUTION: This integrated circuit inductance structure includes a silicon substrate, a planar winding of a conductive track, a resistive layer which is not etched under the winding, an insulation layer between the winding and the resistive layer, and discontinuous conductive sections, individually parallel to a portion of the winding, which is the closest and electrically connected to ground and to the resistive layer.

公开(公告)号：JP2002300543A

公开(公告)日：2002-10-11

申请号：JP2001373734

申请日：2001-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： ALBELLA ARNAUD ,  TAUZIA VINCENT

IPC: H04N5/44 ,  H04B1/16 ,  H04H20/00 ,  H04H60/27 ,  H04N5/445 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/088 ,  H04H1/00

Abstract: PROBLEM TO BE SOLVED: To provide a storage circuit for implementing a method, and a television receiver, including this kind of storage circuit. SOLUTION: A storage circuit (20), of a television receiver for receiving a character broadcasting service, is provided with a data memory (24) for storing at least one received page, and a method for storing the page of the character broadcasting service comprises a step (E1) for extracting a reference number from the received page, a step (E2) for checking whether the received page is a requested page, and a step (E4) for storing the received page. This method comprises a step (E3) for evaluating the contents of the data memory (24) for deciding whether the received page should be stored, depending on the free space of the data memory (24) and the significance of the received page; the evaluation step (E3) is executed, after the checking step (E2); and the storage step (E4) is executed, if the received page nods to be stored.

公开(公告)号：JP2002100680A

公开(公告)日：2002-04-05

申请号：JP2001212949

申请日：2001-07-13

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MORAND YVES ,  PELLOIE JEAN-LUC

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a process for manufacturing a capacitor of an integrated circuit. SOLUTION: At least at a part of an inter-track insulating layer involved in a prescribed metallization stage, two electrodes and dielectric layers of a capacitor are manufactured while a conductive groove which extends the lower part electrode of the capacitor is manufactured. The conductive groove is narrower than the capacitor in cross section while electrically insulated from an upper part electrode. Two conductive pads are manufactured which contact the upper part electrode of the capacitor and the conductive groove, respectively, at an inter-level insulating layer covering the inter-track insulating layer.

公开(公告)号：JP2002033680A

公开(公告)日：2002-01-31

申请号：JP2001140159

申请日：2001-05-10

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC

IPC: G06K17/00 ,  G01S13/75 ,  G01S13/76 ,  G01S13/79 ,  G06K7/00 ,  H04B1/59

Abstract: PROBLEM TO BE SOLVED: To provide a novel control method for a read/write terminal that unsharpens the read/write terminal against a demodulation gap of data received from a transponder entering the field of the read/write terminal. SOLUTION: This invention provides the method for controlling the terminal generating an electromagnetic field that is provided with a circuit to control the phase of a signal from an oscillating circuit and uses a signal to oscillate the oscillation circuit while including a method for comparing a current variable linked to current of the oscillation circuit and (voltage applied to the oscillation circuit with a prescribed value and for detecting the presence of the transponder in the electromagnetic field.

公开(公告)号：JP2002009658A

公开(公告)日：2002-01-11

申请号：JP2001141586

申请日：2001-05-11

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC

IPC: H04B1/59 ,  G06K7/00

Abstract: PROBLEM TO BE SOLVED: To provide a terminal that generates an electromagnetic field for communication with at least one transponder, and to provide a method for controlling this terminal. SOLUTION: The terminal is provided with an oscillation circuit, that is excited by a remote supply signal from the transponder, a phase demodulator for detecting data sent from the transponder, a means for regulating a signal phase of the oscillation circuit of the terminal to be a reference value, a means for measuring a variable linked with a current and a voltage of the oscillation circuit, and a means that compares the present value of the variable with a prescribed value to decide whether the transponder is present.

公开(公告)号：JP2001308758A

公开(公告)日：2001-11-02

申请号：JP2001021513

申请日：2001-01-30

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC

IPC: G06K17/00 ,  G01S13/75 ,  G01S13/76 ,  G01S13/79 ,  G06K7/00 ,  H02J17/00 ,  H04B1/59 ,  H04B5/02

Abstract: PROBLEM TO BE SOLVED: To optimize the power consumption of an electromagnetic transponder read/write terminal. SOLUTION: A terminal for generating an electromagnetic field so as to collaborate with at least one transponder when transponders entered the electromagnetic field of the terminal, includes an oscillating circuit composed for receiving a high frequency alternative current excitation voltage, a circuit to adjust the signal phase of the oscillating circuit in terms of a reference value, a circuit to determine present information related to electromagnetic coupling between the transponder and the terminal, and a circuit to adapt the electromagnetic field electric power according to at least the present information.

公开(公告)号：JP2001244275A

公开(公告)日：2001-09-07

申请号：JP2000283976

申请日：2000-09-19

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

IPC: H01L29/73 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a self-aligned vertical bipolar transistor. SOLUTION: The method for manufacturing the bipolar transistor comprises a process in which a base region 8 having an extrinsic base 800 and an intrinsic base is formed. The method comprises a process which forms an emitter region comprising an emitter block having a comparatively narrow lower part arranged in an emitter window formed above the intrinsic base. When the extrinsic base is formed, the implantation of impurities is executed so as to be self-aligned with respect to the emitter window, by being separated by a predetermined distance from the boundary in the lateral direction of the emitter window on both sides of the emitter window after the emitter window is prescribed and before the emitter block is formed.

公开(公告)号：JP2001229664A

公开(公告)日：2001-08-24

申请号：JP2000296390

申请日：2000-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： MOREAUX CHRISTOPHE

IPC: G06K19/07 ,  G11C7/00

Abstract: PROBLEM TO BE SOLVED: To eliminate the danger that a card fails because of a contact defect between the card and the brush of a card reader. SOLUTION: This input circuit 200 for a memory integrated circuit receives a first binary signal SA transmitted by the direct contact of the card and the reader 150, performs change by first binary data A and outputs a write control signal WR for controlling a memory 140. The input circuit is provided with a control circuit 220 for inspecting the voltage level of the first binary signal SA and outputting a confirmation signal VAL and an inhibition circuit 240 for inhibiting a write command WR when the confirmation signal VAL is inactive.