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公开(公告)号：KR1020170044424A
公开(公告)日：2017-04-25
申请号：KR1020150144096
申请日：2015-10-15
Applicant: 삼성전자주식회사
CPC classification number: G06T7/0004 , G06T5/002 , G06T7/12 , G06T7/62 , G06T2207/10061 , G06T2207/20024 , G06T2207/20048 , G06T2207/20216 , G06T2207/30148
Abstract: 두께측정방법에서는, 제1 막질을포함하는구조에대한원본영상을획득한다. 원본영상에기초하여제1 막질의제1 경계를추출한다. 제1 경계를기초로원본영상을변환하여제1 영상을발생한다. 제1 영상에대한필터링을수행하여제2 영상을발생한다. 제2 영상에기초하여제1 막질의제2 경계를추출한다. 제1 경계및 제2 경계에기초하여제1 막질의두께를연산한다.
Abstract translation: 在厚度测量方法中，获得包括第一膜质量的结构的原始图像。 并基于原始图像提取第一胶片质量的第一边界。 并根据第一个边界转换原始图像以生成第一个图像。 并对第一个图像执行过滤以生成第二个图像。 并基于第二图像提取第一胶片质量的第二边界。 基于第一边界和第二边界计算第一膜的厚度。
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公开(公告)号：KR101700572B1
公开(公告)日：2017-02-01
申请号：KR1020100102586
申请日：2010-10-20
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7835 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/4236 , H01L29/66537 , H01L29/6659 , H01L29/66659 , H01L29/78
Abstract: 반도체기판의활성영역을가로지르는게이트, 상기게이트양 옆의상기활성영역내에형성되며, 서로이격된소오스영역및 드레인영역, 상기소오스영역및 상기드레인영역사이의상기활성영역내에제공되고제1 채널불순물농도를갖는주 채널불순물영역, 및상기드레인영역과인접하는상기활성영역내에형성되며, 상기주 채널불순물영역과같은도전형을갖고, 상기제1 채널불순물농도보다낮은제2 채널불순물농도를갖는저농도채널불순물영역을포함하되, 상기저농도채널불순물영역과상기주 채널불순물영역은공통적으로제1 원소를포함하되, 상기제1 원소는원소주기율표에서의 3족및 5족중 어느하나이고, 상기저농도채널불순물영역은상기제1 원소와다른족(group)의제2 원소를포함하되, 상기제1 원소와다른족(group)은 3족및 5족중 하나인반도체소자가제공된다.
Abstract translation: 提供半导体器件，其包括穿过衬底的有源区的栅极; 源极区域和漏极区域，位于栅极的任一侧上并且彼此间隔开的有源区域中; 在源区和漏区之间的有源区中的主沟道杂质区，并具有第一沟道杂质浓度; 以及与漏极区相邻的有源区中的轻掺杂沟道杂质区。 轻掺杂沟道杂质区具有与主沟道杂质区相同的导电类型和第二沟道杂质浓度，低于第一沟道杂质浓度。 轻掺杂沟道杂质区和主沟道杂质区含有第一元素。 轻掺杂沟道杂质区还包含与第一元素不同的组元素的第二元素。
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公开(公告)号：KR1020120069309A
公开(公告)日：2012-06-28
申请号：KR1020100130807
申请日：2010-12-20
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336 , H01L27/108 , H01L21/8242
CPC classification number: H01L29/1033 , H01L29/513 , H01L29/517 , H01L27/10823 , H01L21/76283 , H01L27/10876 , H01L27/10891
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent deterioration due to thermal electron organic punch-through phenomenon by including asymmetric active regions around a central line of a gate electrode. CONSTITUTION: A device isolation layer(112) is formed on a substrate(110) and defines the device isolation layer. A gate electrode(116) crosses the active region. The active region comprises a first active region and a second active region. The first active region and the second active region are asymmetrical around a central line of the gate electrode.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过在栅电极的中心线周围包括不对称有源区域来防止由于热电子有机穿透现象而导致的劣化。 构成：在衬底（110）上形成器件隔离层（112）并限定器件隔离层。 栅电极（116）穿过有源区。 有源区包括第一有源区和第二有源区。 第一有源区和第二有源区围绕栅电极的中心线是不对称的。
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公开(公告)号：KR1020070088373A
公开(公告)日：2007-08-29
申请号：KR1020070018241
申请日：2007-02-23
Applicant: 삼성전자주식회사
CPC classification number: H04L25/023 , H04L12/28 , H04L27/26
Abstract: An apparatus and a method for channel estimation for data demodulation in a broadband wireless access system are provided to estimate a channel by using a preamble whose phase rotation components is compensated, thereby improving channel estimating performance for FCH(Frame Control Header) and DL-MAP(Downlink-MAP) demodulation. An apparatus for channel estimation in a broadband wireless access system comprises the followings: a channel estimator(305) which performs channel estimation for a received symbol and outputs a channel estimation result; an estimating buffer(315); and a preamble phase compensator(320) which receives a channel estimation result related to the pilot subcarrier of the data symbol from the channel estimator and receives a preamble channel estimation result from the estimating buffer, and calculates a phase rotation value between the received results, and compensates the preamble channel estimation result by using the phase rotation value, and stores the compensated preamble channel estimation result in the estimating buffer.
Abstract translation: 提供了一种用于在宽带无线接入系统中进行数据解调的信道估计的装置和方法，以通过使用补偿相位旋转分量的前同步码来估计信道，从而提高FCH（帧控制报头）和DL-MAP的信道估计性能 （Downlink-MAP）解调。 一种用于宽带无线接入系统中信道估计的装置，包括以下步骤：对接收到的符号进行信道估计并输出信道估计结果的信道估计器（305） 估计缓冲器（315）; 以及前导码相位补偿器（320），其从所述信道估计器接收与所述数据符号的导频子载波相关的信道估计结果，并从所述估计缓冲器接收前导信道估计结果，并且计算所述接收结果之间的相位旋转值， 并且通过使用相位旋转值补偿前导信道估计结果，并将经补偿的前导信道估计结果存储在估计缓冲器中。
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Patent Agency Ranking
公开(公告)号：KR100594085B1
公开(公告)日：2006-06-30
申请号：KR1020040109955
申请日：2004-12-21
Applicant: 삼성전자주식회사
IPC: H04J11/00
CPC classification number: H04L25/0232 , H04L5/0007 , H04L5/0048
Abstract: 본 발명은 직교 주파수 분할 다중 시스템에서, 현재 입력 심볼의 파일럿 부반송파들 각각에 대응하여, 현재 입력 심볼 구간 동안에 인접 파일럿 부반송파들의 채널 추정값을 선형 보간하여 인접 파일럿 부반송파들 사이에 위치하는 데이터 부반송파들에 관한 시간영역 채널 추정을 한다.
직교 주파수 분할 다중(OFDM), 채널 추정, 시간영역, 선형 보간, 파일럿.-
公开(公告)号：KR1020010068391A
公开(公告)日：2001-07-23
申请号：KR1020000000305
申请日：2000-01-05
Applicant: 삼성전자주식회사
Inventor： 박민철
IPC: H03K5/1252
CPC classification number: H03K5/1252 , G11C7/22
Abstract: PURPOSE: A clock stretching circuit is provided which stretches a main clock signal to generate a stabilized inner clock signal. CONSTITUTION: A clock stretching circuit includes a logic circuit(10), the first latch(20), the second latch(30), and a masking logic circuit(40). The logic circuit detects if the first stretching signal or the second stretching signal is activated for the first or second period and generates a detection signal. The first latch latches the detection signal at the first shift time of the main clock signal. The second latch latches the activated detection signal at the second shift time of the main clock signal when the detection signal output from the first latch maintains an activation level for a predetermined period of time. The masking logic circuit outputs the main clock signal as an inner clock signal while maintaining the inner clock signal at the first level while the detection signal output from the first latch has the activated level.
Abstract translation: 目的：提供一个时钟延长电路，其延伸主时钟信号以产生稳定的内部时钟信号。 构成：时钟延伸电路包括逻辑电路（10），第一锁存器（20），第二锁存器（30）和屏蔽逻辑电路（40）。 逻辑电路检测第一延伸信号或第二拉伸信号是否在第一或第二周期被激活，并产生检测信号。 第一个锁存器在主时钟信号的第一个移位时间锁存检测信号。 当从第一锁存器输出的检测信号保持预定时间段的激活电平时，第二锁存器在主时钟信号的第二移位时间锁存激活的检测信号。 屏蔽逻辑电路输出主时钟信号作为内部时钟信号，同时将内部时钟信号保持在第一电平，同时从第一锁存器输出的检测信号具有激活电平。
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公开(公告)号：KR1020000026572A
公开(公告)日：2000-05-15
申请号：KR1019980044165
申请日：1998-10-21
Applicant: 삼성전자주식회사
Inventor： 박민철
IPC: H01L27/00
Abstract: PURPOSE: A full adder of the semiconductor device is provided to reduce the delay time, the electric power consumption and the layout area by taking the advantage of the CMOS LOGIC structure and the CPL structure. CONSTITUTION: A full adder of the semiconductor device comprises an adding up means(100), a digit rounding up means(200) and an inverter(11). The full adder outputs first and second signals corresponding to the rounded digit and the added up numbers of the input signals. The full adder includes the inverter and a plurality of MOS transistors of exclusive or gate type. The digit rounding up means includes the inverter and a plurality of MOS transistors of CMOS LOGIC type. The adding up means(100) of CPL structure reduces the time delay and power consumption by reducing the input capacitance.
Abstract translation: 目的：提供半导体器件的全加器，通过利用CMOS LOGIC结构和CPL结构来减少延迟时间，功耗和布局面积。 构成：半导体器件的全加器包括加法装置（100），数字舍入装置（200）和反相器（11）。 全加器输出对应于舍入数字的第一和第二信号以及输入信号的相加数。 全加器包括反相器和多个独占或门类型的MOS晶体管。 数字舍入装置包括反相器和CMOS LOGIC型的多个MOS晶体管。 CPL结构的加法装置（100）通过降低输入电容来减少时间延迟和功耗。
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公开(公告)号：KR1020000020887A
公开(公告)日：2000-04-15
申请号：KR1019980039678
申请日：1998-09-24
Applicant: 삼성전자주식회사
IPC: H01L21/24
Abstract: PURPOSE: A method of manufacturing a semiconductor device is provided to minimize the time loss caused during a process for forming Co into salicide. CONSTITUTION: A method of manufacturing a semiconductor device comprises the steps of: consecutively performing a first heat treatment for forming Co manufactured within the temperature range of 450 to 500 deg.C on a semiconductor substrate having patterns like a gate into CoSi within the same range of temperature; eliminating Co having imperfect combination state due to the first heat treatment by using sulfuric acid; and performing a second heat treatment within the temperature range of 800 to 900 deg.C to form the CoSi manufactured on the semiconductor substrate into CoSi2.
Abstract translation: 目的：提供一种制造半导体器件的方法，以最小化在将自由基形成Co的过程中引起的时间损失。 构成：制造半导体器件的方法包括以下步骤：在具有类似栅极的半导体衬底的相同范围内的CoSi中连续执行在450至500℃的温度范围内制造的Co的第一热处理 的温度; 消除由于使用硫酸的第一次热处理而导致的不完全组合状态的Co; 在800〜900℃的温度范围内进行第二次热处理，在半导体基板上形成CoSi2。
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公开(公告)号：KR1020160023484A
公开(公告)日：2016-03-03
申请号：KR1020140109961
申请日：2014-08-22
Applicant: 삼성전자주식회사
IPC: A61B6/00
CPC classification number: A61B6/502 , A61B6/0414 , A61B6/4464 , A61B6/465 , A61B6/488 , A61B6/542
Abstract: 일부실시예에따른엑스선영상장치는, 대상체에제1 선량의엑스선을조사하여제1 영상정보를획득하는엑스선촬영부; 상기제1 영상정보를기초로상기대상체의밀도이상의여부를판단하는제어부; 상기밀도이상의여부를표시하는출력부를포함한다.
Abstract translation: 根据本发明实施例的X射线图像装置包括：X射线摄影单元，用于通过向对象照射第一剂量X射线来获得第一图像信息; 控制单元，用于基于第一图像信息确定对象的浓度异常; 以及用于显示密度异常的输出单元。
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