-
公开(公告)号：KR1020080112011A
公开(公告)日：2008-12-24
申请号：KR1020070060686
申请日：2007-06-20
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49558 , H01L23/16 , H01L23/3107 , H01L2225/1029 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
Abstract: A semiconductor package including a thermal stress absorbent member is provided to improve fatigue life preventing exfoliation or crack generation of a solder land and influencing second level reliability of a semiconductor package by preparing a thermal stress absorbent member. Semiconductor packages(110,120) comprises a semiconductor chip(125), an encapsulating material(128), lead portions(310, 320), a thermal stress absorbent member(700). The encapsulating material surrounds the semiconductor chip. The lead portion is exposed to outside. The thermal stress absorbent member absorbs the thermal stress of the semiconductor chip or the encapsulating material in order to be delivered to the lead portion.
Abstract translation: 提供一种包括热应力吸收件的半导体封装，以通过制备热应力吸收件来改善疲劳寿命，从而防止焊盘的剥离或裂纹产生以及影响半导体封装的第二级可靠性。 半导体封装（110,120）包括半导体芯片（125），封装材料（128），引线部分（310,320），热应力吸收部件（700）。 封装材料围绕半导体芯片。 引线部分暴露在外面。 热应力吸收部件吸收半导体芯片或封装材料的热应力，以便被输送到引线部分。
-
公开(公告)号：KR100734264B1
公开(公告)日：2007-07-02
申请号：KR1020050052009
申请日：2005-06-16
Applicant: 삼성전자주식회사
IPC: H01L23/52
CPC classification number: H01L25/105 , H01L23/49816 , H01L23/49827 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2225/1094 , H01L2924/01327 , H01L2924/14 , H01L2924/15159 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
Abstract: An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of the board. The land pin may be electrically connected to the integrated circuit chip.
-
公开(公告)号：KR1020170027069A
公开(公告)日：2017-03-09
申请号：KR1020150123515
申请日：2015-09-01
Applicant: 삼성전자주식회사
CPC classification number: H01L22/34 , G01R31/2856 , G01R31/2884 , H01L21/67288 , H01L23/585
Abstract: 반도체칩은반도체기판및 크랙감지회로를포함할수 있다. 상기반도체칩은회로구조물을포함할수 있다. 크랙감지회로는상기회로구조물을둘러싸도록상기반도체기판내에형성된메인라인들, 및상기반도체기판의모서리들에서상기메인라인들을연결하는챔퍼라인들을포함할수 있다. 상기챔퍼라인들각각은서로직교하는상기메인라인들중에서어느하나의메인라인과제 1 각도를이루고나머지메인라인과제 1 각도보다넓은제 2 각도를이룰수 있다. 따라서, 크랙이크랙감지회로를지나서회로구조물로전파되지않는다면, 정상인회로구조물을갖는반도체칩을불량으로판정하는오류를방지할수 있다.
Abstract translation: 半导体芯片可以包括半导体衬底和裂纹检测电路。 半导体衬底可以包括电路结构。 裂纹检测电路可以包括主线和倒角线。 主线可以形成在半导体衬底中以包围电路结构。 倒角线可以形成在半导体衬底的角部。 倒角线可以连接在主线之间。 可以在每个倒角线和彼此垂直的两个主线中的任一个之间形成第一角度。 可以在每个倒角线和另一个主线之间形成比第一角宽的第二角度。 因此，尽管通过两次切割晶片的过程可能在半导体基板的拐角处产生裂纹，但是裂纹检测电路可能不会检测到裂纹。
-
公开(公告)号：KR1020100045193A
公开(公告)日：2010-05-03
申请号：KR1020080104266
申请日：2008-10-23
Applicant: 삼성전자주식회사
CPC classification number: H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/73265 , H01L2225/06562 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: PURPOSE: A semiconductor package device is provided to prevent short-circuit between leads by combining an exposure direction of a lead in one direction. CONSTITUTION: At least one first semiconductor chip(1) is provided. At least one second semiconductor chip(2) is located in the lower direction of the first semiconductor chip. A sealant(3) protects the first semiconductor chip and the second semiconductor chip. One end of the first lead(11) is electrically connected to the first semiconductor chip. The other end part of the first lead is exposed to the outside of the sealant. A second lead(12) is electrically connected to the second semiconductor chip.
Abstract translation: 目的：提供一种半导体封装器件，用于通过在一个方向上组合引线的曝光方向来防止引线之间的短路。 构成：提供至少一个第一半导体芯片（1）。 至少一个第二半导体芯片（2）位于第一半导体芯片的下方。 密封剂（3）保护第一半导体芯片和第二半导体芯片。 第一引线（11）的一端电连接到第一半导体芯片。 第一引线的另一端部暴露于密封剂的外侧。 第二引线（12）电连接到第二半导体芯片。
-
公开(公告)号：KR1020070006291A
公开(公告)日：2007-01-11
申请号：KR1020050061504
申请日：2005-07-08
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2924/15311 , H01L2924/00014 , H01L2924/00 , H05K3/4602 , H01L23/12 , H01L23/49816 , H05K1/0271 , H05K2201/068
Abstract: A wiring board and a semiconductor device having the same are provided to suppress bending or deformation of the wiring board at a hot process by forming a core layer opposite to a surface on which a semiconductor chip is formed. A wiring board includes a board body(155) consisting of a core layer(154) formed on a center portion and an insulation layer(153) deposited on upper and lower surfaces of the core layer. The core layer is formed in the insulation layer when the core layer is positioned towards a surface on which a semiconductor chip(110) is not formed. The core layer is made of a material having thermal expansion coefficient lower than that of the insulation layer.
Abstract translation: 通过形成与形成半导体芯片的表面相对的芯层，设置有布线基板及具有该布线基板的半导体装置，以抑制热加工时的布线基板的弯曲变形。 布线板包括由形成在中心部分的芯层（154）和沉积在芯层的上表面和下表面上的绝缘层（153）组成的板体（155）。 当芯层朝向未形成半导体芯片（110）的表面定位时，芯层形成在绝缘层中。 芯层由热膨胀系数低于绝缘层的热膨胀系数的材料制成。
-
Patent Agency Ranking
公开(公告)号：KR1020060131506A
公开(公告)日：2006-12-20
申请号：KR1020050052009
申请日：2005-06-16
Applicant: 삼성전자주식회사
IPC: H01L23/52
CPC classification number: H01L25/105 , H01L23/49816 , H01L23/49827 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2225/1094 , H01L2924/01327 , H01L2924/14 , H01L2924/15159 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
Abstract: An IC package and an IC module are provided to secure an aiming reliability for a long time by stabilizing a connection state between a post pin and a land pin using a metal connection or a mechanical connection. An IC chip(321) is mounted on a substrate(311). A post pin(341) is formed on one surface of the substrate. The post pin is made of a first metallic material. The post pin is electrically connected with the IC chip. A land pin(351) is formed on the other surface of the substrate. The land pin is made of a second metallic material. The land pin is electrically connected with the IC chip. The land pin and the post pin are electrically connected with each other through a predetermined metal(361) of a via hole, wherein the via hole is formed through the substrate.
Abstract translation: 提供IC封装和IC模块以通过使用金属连接或机械连接来稳定柱形销和平台销之间的连接状态来长时间确保目标可靠性。 IC芯片（321）安装在基板（311）上。 在基板的一个表面上形成柱销（341）。 柱销由第一金属材料制成。 后引脚与IC芯片电连接。 在基板的另一个表面上形成有一个引脚（351）。 地脚销由第二金属材料制成。 接地引脚与IC芯片电连接。 接地引脚和引脚通过通孔的预定金属（361）彼此电连接，其中通孔穿过基板形成。
-
公开(公告)号：KR1020170122494A
公开(公告)日：2017-11-06
申请号：KR1020160051528
申请日：2016-04-27
Applicant: 삼성전자주식회사
IPC: H01L21/78 , H01L21/76 , H01L21/3213 , H01L21/768
CPC classification number: H01L23/562 , H01L21/78 , H01L23/585 , H01L2224/16225 , H01L2924/181 , H01L2924/00012
Abstract: 본발명의기술적사상은메인칩 영역과상기메인칩 영역를둘러싸는스크라이브레인영역을포함하고, 상기스크라이브레인영역은상기메인칩 영역을둘러싸는제1 영역및 상기제1 영역을둘러싸는제2 영역을포함하는반도체기판, 상기반도체기판상의절연막, 상기제1 영역내의상기절연막상에형성되며, 상기메인칩 영역의가장자리를따라배열된제1 엠보싱구조체들을포함하는제1 엠보싱패턴, 상기제2 영역내의상기절연막상에형성되며, 상기메인칩 영역의가장자리를따라배열된제2 엠보싱구조체들을포함하는제2 엠보싱패턴, 및상기제1 영역내의상기절연막내에형성되며, 상기절연막의두께방향으로연장하고상기제1 엠보싱구조체들과상기절연막의두께방향으로정렬되는댐 구조체들을포함하는반도체장치를제공한다.
Abstract translation: 本发明的技术特征是主芯片区域和所述主芯片youngyeokreul环绕包括划片线区域，所述划片线区周围环绕所述第一区域和所述第一区域到所述第二区域中的主芯片区域 所述在第一区域中绝缘膜，在沿主芯片区域的边缘布置在第一压花图案和包括第一压印结构的第二区域的半导体衬底上的绝缘膜，其包括在半导体衬底，形成在 在绝缘膜形成，形成于第二压花图案，并在其中包括沿主芯片区域的边缘布置在第二压花结构的第一区域的绝缘膜，以及在绝缘膜，其中的厚度方向上延伸 以及与第一压花结构和绝缘膜的厚度方向对齐的堰结构。
-
公开(公告)号：KR100905719B1
公开(公告)日：2009-07-01
申请号：KR1020070060686
申请日：2007-06-20
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49558 , H01L23/16 , H01L23/3107 , H01L2225/1029 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
Abstract: 반도체 칩; 상기 반도체 칩을 감싸는 봉지재; 외부로 노출되는 리드부; 상기 반도체 칩 또는 상기 봉지재의 열응력이 상기 리드부로 전달되지 않도록 흡수하는 열응력 흡수 부재; 를 포함하는 것을 특징으로 하는 반도체 패키지가 개시된다.
-
公开(公告)号：KR1020070010916A
公开(公告)日：2007-01-24
申请号：KR1020050065906
申请日：2005-07-20
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/11 , H01L23/49816 , H01L23/522 , H01L2224/03914
Abstract: An interconnection substrate for fabricating a BGA package having a ball land structure is provided to improve interfacial junction reliability by increasing the contact area between a ball land and a solder ball. A metal interconnection with a predetermined pattern is formed on a substrate body(310). Ball lands(320) are joined to a solder ball as an external terminal, formed next to the metal interconnection. A first passivation layer(331) is formed on the front surface of the substrate body to protect the metal interconnection and the ball land, having a first opening exposing a predetermined part of the ball land. A second passivation layer(332) is formed on the first passivation layer to protect the exposed part of the ball land from the outside, having a second opening in a corresponding position to the exposed part of the ball land. The ball land has a mixed ball land structure, including first and second ball lands(321,322). The first ball land is formed in the first passivation layer. The lower part(322b) of the second ball land is formed on the first ball land, and the upper part(322a) of the second ball land continuous to the lower part protrudes to a portion over the first passivation layer through the first opening. The second opening has a greater diameter than that of the solder ball to prevent the second passivation layer from coming in contact with the solder ball. The second ball land is of a cylindrical type whose upper and lower diameters are the same.
Abstract translation: 提供了一种用于制造具有球面结构的BGA封装的互连衬底，以通过增加球焊盘和焊球之间的接触面积来改善界面接合可靠性。 具有预定图案的金属互连形成在基板主体（310）上。 焊接区域（320）作为外部端子与焊球接合，形成在金属互连附近。 第一钝化层（331）形成在基板主体的前表面上，以保护具有第一开口的金属互连和球接地，露出预定部分的球区。 在第一钝化层上形成第二钝化层（332），以保护球露出部分的外露，其中第二开口处于与球面露出部分相对应的位置。 球场有一个混合的球场结构，包括第一和第二个球场（321,322）。 第一球形区域形成在第一钝化层中。 第二球形地面的下部（322b）形成在第一球台上，并且与下部连接的第二球台的上部（322a）通过第一开口突出到第一钝化层上方的部分。 第二开口具有比焊球更大的直径，以防止第二钝化层与焊球接触。 第二球场是圆柱形的，其上下直径相同。
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.022 seconds)
