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    전자 장치 및 그것의 온도 제어 방법
    2.
    发明公开
    전자 장치 및 그것의 온도 제어 방법 无效
    电子器件及其温度控制方法

    公开(公告)号：KR1020130074293A

    公开(公告)日：2013-07-04

    申请号：KR1020110142288

    申请日：2011-12-26

    Applicant: 삼성전자주식회사

    Inventor： 김재춘 ,  김지철 ,  백형길 ,  조은석

    IPC: G05D23/19

    CPC classification number: H01L23/34 ,  G06F1/203 ,  G06F1/206 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: PURPOSE: Electronic device and temperature control method thereof are provided to guarantee reliability of an electronic device by operating a multistage function mode according to a temperature level. CONSTITUTION: Whether temperature of a target location increases greater than first reference temperature is detected (S120). When the temperature of the target location is greater than the first reference temperature, an operation parameter of the electronic device is configured to correspond to a first operation mode. Whether the temperature of the target location increases and becomes greater than second reference temperature greater than the first reference temperature is detected (S140). When the temperature of the target location is greater than the second reference temperature, the operation parameter of the electronic device is configured to correspond to a second operation mode slower than the first operation mode.

    Abstract translation: 目的：提供电子设备及其温度控制方法，以通过根据温度水平操作多级功能模式来保证电子设备的可靠性。 构成：检测到目标位置的温度是否增加大于第一参考温度（S120）。 当目标位置的温度大于第一参考温度时，电子设备的操作参数被配置为对应于第一操作模式。 检测目标位置的温度是否增加并且变得大于大于第一参考温度的第二参考温度（S140）。 当目标位置的温度大于第二参考温度时，电子设备的操作参数被配置为对应于比第一操作模式慢的第二操作模式。

    증가된 결합 신뢰성을 갖는 반도체 모듈들
    3.
    发明授权
    증가된 결합 신뢰성을 갖는 반도체 모듈들 失效
    具有增强联接可靠性的半导体模块

    公开(公告)号：KR100834442B1

    公开(公告)日：2008-06-04

    申请号：KR1020070004896

    申请日：2007-01-16

    Applicant: 삼성전자주식회사

    Inventor： 백형길

    IPC: H01L21/60 ,  H01L23/48 ,  H05K1/18

    CPC classification number: H05K1/0271 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/181 ,  H05K3/4626 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2224/0401

    Abstract: A semiconductor module having enhanced joint reliability is provided to reduce thermal deformation caused by a difference between thermal expansion coefficients by using a buffer layer. An upper package(120) includes an upper semiconductor chip. A printed circuit board(110) includes upper internal terminals to be coupled with the upper package. A plurality of conductive coupling structures(145) are formed to connect electrically the upper package with the printed circuit board. The printed circuit board includes at least two substrate layers and at least one buffer layer(200) inserted into a predetermined region between the substrate layers. The buffer layer includes at least one of materials having modulus of 10MPa to 1 GPa.

    Abstract translation: 提供了具有增强的接头可靠性的半导体模块，以减少由于使用缓冲层而导致的热膨胀系数之差引起的热变形。 上封装（120）包括上半导体芯片。 印刷电路板（110）包括要与上部封装件连接的上部内部端子。 形成多个导电耦合结构（145）以将上部封装与印刷电路板电连接。 印刷电路板包括至少两个基底层和插入到基底层之间的预定区域中的至少一个缓冲层（200）。 缓冲层包括模量为10MPa至1GPa的材料中的至少一种。

    볼 그리드 어레이 유형의 적층 패키지
    5.
    发明公开
    볼 그리드 어레이 유형의 적층 패키지 失效
    堆叠阵列类型堆叠

    公开(公告)号：KR1020070095502A

    公开(公告)日：2007-10-01

    申请号：KR1020050096659

    申请日：2005-10-13

    Applicant: 삼성전자주식회사

    Inventor： 박상욱 ,  백형길

    IPC: H01L23/12

    CPC classification number: H01L23/49833 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A stack package of ball grid array type is provided to prevent effectively the deflection of the package due to differences in the coefficients of thermal expansion. A package includes a first package(31a) and a second package(31b) stacked on the first package. Each of the first and the second packages has a semiconductor chip(33a,33b) with an active surface and a non-active surface. A first circuit substrate(34a,34b) is located on the active surface, and a second circuit substrate(35a,35b) is located on the non-active surface. A first internal connection member electrically connects the semiconductor chip with the first circuit substrate, and a second internal connection member electrically connects the first circuit substrate with the second circuit substrate. An external contact member is formed on the first circuit substrate.

    Abstract translation: 提供球栅阵列型的堆叠封装，以有效地防止由于热膨胀系数的差异而引起的封装的挠曲。 包装包括堆叠在第一包装上的第一包装（31a）和第二包装（31b）。 第一和第二封装中的每一个具有具有活性表面和非活性表面的半导体芯片（33a，33b）。 第一电路基板（34a，34b）位于有源表面上，第二电路基板（35a，35b）位于非活动表面上。 第一内部连接构件将半导体芯片与第一电路基板电连接，第二内部连接构件将第一电路基板与第二电路基板电连接。 外部接触部件形成在第一电路基板上。

    반도체 장치
    6.
    发明公开
    반도체 장치 审中-实审
    半导体器件

    公开(公告)号：KR1020170133146A

    公开(公告)日：2017-12-05

    申请号：KR1020160064223

    申请日：2016-05-25

    Applicant: 삼성전자주식회사

    Inventor： 백남규 ,  조윤래 ,  백형길 ,  김선대

    IPC: H01L21/768 ,  H01L21/78 ,  H01L21/76 ,  H01L21/283 ,  H01L21/3213

    CPC classification number: H01L23/562 ,  H01L22/34 ,  H01L23/585

    Abstract: 본발명의기술적사상에의한반도체장치는, 가드링에의해한정되는메인칩 영역, 메인칩 영역내에메인칩 영역의중심부를둘러싸도록형성된크랙감지회로, 및메인칩 영역의코너부분에가드링과크랙감지회로로구획되는챔퍼영역을포함하는반도체기판, 메인칩 영역내의반도체기판상에형성된게이트구조체, 챔퍼영역내의게이트구조체상에형성되며, 순차적으로다른길이를갖고서로평행하게배열된복수의금속패턴구조체, 및복수의금속패턴구조체를덮도록형성된절연막을포함한다.

    Abstract translation: 根据本发明的技术特征的半导体装置，其主要由保护环晶粒区域所定义，形成在主芯片裂缝检测电路，以包围主芯片区域的中心部分中的区域中，并且所述保护环的主芯片面积和在角部的裂纹 包括由所述感测电路中，主芯片面积栅极结构划分的倒角区域的半导体衬底，被形成在所述倒角区域中的栅极结构形成于所述半导体衬底上，在序列中的多个已布置在相互平行的金属图案的不同长度 并形成绝缘膜以覆盖多个金属图案结构。

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