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公开(公告)号：KR1020010037189A
公开(公告)日：2001-05-07
申请号：KR1019990044571
申请日：1999-10-14
Applicant: 삼성전자주식회사
IPC: G06F7/50
Abstract: PURPOSE: The full adder is provided to reduce a size of a layout although the speed of the layout is rapid. CONSTITUTION: A full adder comprises inverters(12,18,20,34,36), a NAND gate(14), a NOR gate(16), a PMOS transistor(22), an NMOS transistor(24) and transmitting gates(26¯32). The first inverter(18) comprises a PMOS transistor(40) having an electric pass formed between output terminals of the power voltage(VDD) and the NOR gate(16) successively in serial and a gate being controlled by output of the NAND gate(14) and an NMOS transistor(42). The second inverter(20) comprises a PMOS transistor(44) having an electric pass formed between output terminals of the NAND gate(14) and grounding voltage successively in serial and a gate being controlled by output of the NOR gate(16) and an NMOS transistor(46). The first inverter(18) converts the output signal of the NAND gate(14) while the output signal of the NOR gate(16) is low level. The second inverter(20) converts the output signal of the NOR gate(16) while the output signal of the NAND gate(14) is high level. The PMOS transistor(22) includes a drain connected to the output terminal of the NOR gate(16), a source connected to the output terminal of the first inverter(18) and a gate controlled by the first input signal. The NMOS transistor(24) includes a drain connected to the output terminal of the NAND gate(14), a source connected to the output terminal of the second inverter(20) and a gate controlled by the second input signal. The first transmitting gate(26) has an input terminal connected to an output terminal of the first inverter(18) and an output terminal connected to an input terminal of the fourth inverter(34). The first transmitting gate(26) is controlled by the carry input signal converted through the third inverter(12), and transmits the output of the first inverter(18) to the fourth inverter(34).
Abstract translation: 目的：提供全加器以减少布局的大小，尽管布局的速度很快。 构成：全加器包括反相器（12,18,20,34,36），与非门（14），或非门（16），PMOS晶体管（22），NMOS晶体管（24）和发射门极 2632）。 第一反相器（18）包括PMOS晶体管（40），其具有在串联的电源电压（VDD）和NOR门（16）的输出端之间形成的电通路，栅极由NAND门的输出 14）和NMOS晶体管（42）。 第二反相器（20）包括PMOS晶体管（44），其具有在NAND门（14）的输出端和串联连接的接地电压之间形成的电通路，栅极由NOR门（16）的输出控制， NMOS晶体管（46）。 当NOR门（16）的输出信号为低电平时，第一反相器（18）转换NAND门（14）的输出信号。 第二反相器（20）在NAND门（14）的输出信号为高电平时转换NOR门（16）的输出信号。 PMOS晶体管（22）包括连接到或非门（16）的输出端的漏极，连接到第一反相器（18）的输出端的源极和由第一输入信号控制的栅极。 NMOS晶体管（24）包括连接到NAND门（14）的输出端的漏极，连接到第二反相器（20）的输出端的源极和由第二输入信号控制的栅极。 第一发送栅极（26）具有连接到第一反相器（18）的输出端子的输入端子和与第四反相器（34）的输入端子连接的输出端子。 第一发送门（26）由通过第三逆变器（12）转换的进位输入信号控制，并将第一反相器（18）的输出发送到第四反相器（34）。
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公开(公告)号：KR1019980026885A
公开(公告)日：1998-07-15
申请号：KR1019960045451
申请日：1996-10-11
Applicant: 삼성전자주식회사
IPC: G06F7/52
Abstract: 본 발명은 디지탈 신호 처리 분야의 하드웨어 연산장치중에서 6-2 압축기로 구성한 54*54 비트 승산기를 개시한다.
54 비트의 승수와 비승수를 직접 입력하는 직접 엔코더부(Direct Encoder)와 부분곱들을 연속적으로 가산하여 압축하는 압축부와 캐리 전송 지연을 줄이기 위하여 캐리 선택 가산기를 사용하여 곱을 출력하는 최종 가산기(Final Adder)를 포함하는 6-2 압축기로 구성한 54*54 비트 승산기에 있어서 압축부의 6-2 압축기(Compressor)는 제1 전가산기와 제2 전가산기(Full Adder)와 제3 전가산기와 제4 전가산기로 구성한다.
6-2 압축기로 구성한 54*54 비트 승산기는 4-2압축기 3개로 구성된 것보다 전가산기의 회로가 간단하기 때문에 회로내에 들어가는 트랜지스터의 수가 줄어들어 전송단을 줄일 수 있고 에너지 절약형 패스 트랜지스터 로직을 사용하므로써 고속동작을 하면서도 저전력 소비가 가능한 회로 크기가 소형화 되는 효과를 제공한다.-
公开(公告)号：KR1019980021745A
公开(公告)日：1998-06-25
申请号：KR1019960040692
申请日：1996-09-18
Applicant: 삼성전자주식회사
IPC: G11C7/00
Abstract: 본 발명은 출력 버퍼에 관한 것으로서, 특히 CMOS 디지털 회로 또는 아날로그와 디지털 신호가 함께 사용되는 회로에 사용되는 낮은 스위칭 노이즈를 갖는 CMOS 출력 버퍼에 관한 것이다.
본 발명에 따른 낮은 스위칭 노이즈를 갖는 출력 버퍼는, VDD 전원과 VSS 사이에 PMOS 트랜지스터와 NMOS 트랜지스터가 직렬연결된 복수의 제1 내지 제N버퍼단이 병렬로 접속되며, 상기 제1버퍼단중에서 PMOS 게이트와 제2버퍼단의 PMOS 게이트 사이에는 지연소자가 접속되고, 상기 제2버퍼단중에서 NMOS 게이트와 다른 버퍼단의 NMOS 게이트 사이에는 지연소자가 접속되며, 상기 제1 내지 제2버퍼단의 PMOS 드레인과 NMOS 소스 접점부와 나머지 버퍼들의 PMOS 드레인과 NMOS 소스 접점부들을 공통으로 접속하여 출력단자로 구성함이 바람직하다.
상술한 바와 같이 본 발명에 스위칭 노이즈 출력 버퍼는 병렬로 접속된 버퍼사이에 지연소자를 접속하여 입력신호가 지연시간을 갖고 각 드라이버 버퍼에 인가됨으로써, 급격한 레벨변화에 따른 스위칭 노이즈를 억제하는 기능을 제공한다.-
公开(公告)号：KR101584785B1
公开(公告)日：2016-01-13
申请号：KR1020090004944
申请日：2009-01-21
Applicant: 삼성전자주식회사
Abstract: 본발명의실시예에따른아날로그-디지털컨버터는폴딩구조를이용하는아날로그-디지털컨버터에필요한스위칭블락을제거함으로써고속의데이터처리를안정적으로수행할수 있고, 저전력구동, 및소면적특성을갖는다.
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公开(公告)号：KR1020020022159A
公开(公告)日：2002-03-27
申请号：KR1020000054797
申请日：2000-09-19
Applicant: 삼성전자주식회사
IPC: H03M1/18
CPC classification number: H03M1/129 , H03M1/14 , H03M1/205 , H03M2201/65
Abstract: PURPOSE: A folding interpolation analog/digital converter is provided to exactly correct an analog signal beyond an input range at a digital output terminal. CONSTITUTION: A reference voltage generator(10) generates a plurality of reference voltages having different levels. A plurality of folders(20) each receives an input analog signal and the plurality of reference voltages and outputs a folding signal. An interpolation section(30) outputs folding signals having an additional intersection of the same intervals based on folding signals generated by two adjacent folders. A comparator(40) compares an output signal of the interpolation section(30) with a reference signal and output a comparison result. An encoder(50) encodes the comparison result and outputs least significant bits. An input range excess detecting folder(60) receives the input analog signal and the reference voltage and outputs an analog input range excess detecting signal and an enable signal. An error correcting section(70) logically combines the analog input range excess detecting signal and enable signal from the input range excess detecting folder(60) and a folding signal and outputs an error correcting signal.
Abstract translation: 目的：提供折叠插补模拟/数字转换器，以精确校正模拟信号超出数字输出端子的输入范围。 构成：参考电压发生器（10）产生具有不同电平的多个参考电压。 多个文件夹（20）各自接收输入模拟信号和多个参考电压并输出折叠信号。 内插部（30）基于由两个相邻的文件夹生成的折叠信号输出具有相同间隔的附加交点的折叠信号。 比较器（40）将插值部（30）的输出信号与基准信号进行比较，并输出比较结果。 编码器（50）对比较结果进行编码并输出最低有效位。 输入范围过量检测文件夹（60）接收输入的模拟信号和参考电压，并输出模拟输入范围过量检测信号和使能信号。 误差校正部（70）逻辑地组合来自输入范围过量检测文件夹（60）的模拟输入范围过量检测信号和使能信号和折叠信号，并输出纠错信号。
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Patent Agency Ranking
公开(公告)号：KR1020010054850A
公开(公告)日：2001-07-02
申请号：KR1019990055834
申请日：1999-12-08
Applicant: 삼성전자주식회사
IPC: G11C7/00
CPC classification number: H03K3/356139 , H03K3/356156 , H03K3/356191
Abstract: PURPOSE: A high speed latch is provided to remove a kick-back effect generated in a conventional latch, and to compensate a defect by a low speed charge and discharge. CONSTITUTION: A supply power control part(310) outputs the first and the second control power supply voltage according to a clock signal applied to a gate of one of P channel MOS transistors(P1,P0), and has P channel MOS transistors(P1,P3,P2,P0) connected in parallel each other and a supply voltage(VDD) is applied to each source terminal. The first input part(320) transmits an input signal(inn) according to the clock signal, and the second input part(330) transmits an input signal(inp) according to the clock signal. A differential current formation part(340) comprises a unit where N channel MOS transistors(N0,N2) are connected in parallel and the first control voltage is applied to each drain and the first control voltage and the input signal(inn) are applied to each gate, and also comprises a unit where N channel MOS transistors(N1,N3) are connected in parallel and the second control voltage is applied to each source and the second control voltage and the input signal(inp) are applied to each gate. And, a current source(360) is an N channel transistor(N5) which is connected to the drain of the differential current formation part and where a source is grounded and the clock signal is applied to a gate. And, the first and the second output part(INV1,INV2) outputs a signal state by being connected between the supply power control part and the first and the second switching.
Abstract translation: 目的：提供高速闩锁以消除常规闩锁中产生的反冲击效应，并通过低速充电和放电补偿缺陷。 构成：供电电源控制部（310）根据施加到P沟道MOS晶体管（P1，P0）之一的栅极的时钟信号输出第一和第二控制电源电压，并具有P沟道MOS晶体管（P1 ，P3，P2，P0）并且将电源电压（VDD）施加到每个源极端子。 第一输入部（320）根据时钟信号发送输入信号（inn），第二输入部（330）根据时钟信号发送输入信号（inp）。 差动电流形成部分（340）包括并联连接N沟道MOS晶体管（N0，N2）并且将第一控制电压施加到每个漏极并且将第一控制电压和输入信号（inn）施加到 并且还包括并联连接N沟道MOS晶体管（N1，N3）并且将第二控制电压施加到每个源并且将第二控制电压和输入信号（inp）施加到每个栅极的单元。 并且，电流源（360）是N沟道晶体管（N5），其连接到差分电流形成部分的漏极，源极接地并且时钟信号施加到栅极。 并且，第一和第二输出部分（INV1，INV2）通过连接在供电功率控制部分与第一和第二切换之间输出信号状态。
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公开(公告)号：KR1020010054849A
公开(公告)日：2001-07-02
申请号：KR1019990055833
申请日：1999-12-08
Applicant: 삼성전자주식회사
IPC: H03M7/00
Abstract: PURPOSE: A condition selection encoder and an encoding method thereof are provided to calculate a wanted value using relatively fast binary signals after setting up lower binary values of all conditions in advance. CONSTITUTION: In the encoder based conditional selection, a switching unit(560) switches the signal level status by converting the return-to-zero signal to non-return-to-zero signal. A block unit(510-540) divides input signals by bit unit and calculate all possible chances having any of the bit units. An LSB selecting unit(550) produces a binary value by selecting one among the bit units corresponding to the combination of binary values. A D flip-flop unit(590) produces the binary value selected at the LSB selecting unit(550) and other binary values.
Abstract translation: 目的：提供条件选择编码器及其编码方法，以便在预先设置所有条件的较低二进制值之后使用相对较快的二进制信号计算所需值。 构成：在基于编码器的条件选择中，切换单元（560）通过将归零信号转换为非归零信号来切换信号电平状态。 块单元（510-540）通过比特单位划分输入信号，并计算具有任何比特单元的所有可能机会。 LSB选择单元（550）通过选择与二进制值的组合相对应的比特单元中的一个来产生二进制值。 D触发器单元（590）产生在LSB选择单元（550）处选择的二进制值和其他二进制值。
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公开(公告)号：KR1020010025784A
公开(公告)日：2001-04-06
申请号：KR1019990036806
申请日：1999-09-01
Applicant: 삼성전자주식회사
IPC: H03K19/00
Abstract: PURPOSE: A shifter based on the left shift structure is provided to prevent the error occurring when the amounts of shifts and the numbers of input of the left and right shifts are not the same. CONSTITUTION: A shifter(100) based on left shift structure includes an input buffer(20), a MASK decoder(30), a MASK generator(40), a shift array(50), an output buffer(60), a scale element decoder(70) and an option decoder(50). Here, the shift array(50) has a structure only for left shifting. And the shifting occurs after all other operations such as MASK generation are finished. The MASK generator(40) forms patterns to fill the remaining bits after shifting. The option decoder(80) decodes a control signal used for choosing among patterns formed by the MASK generator(40). And an extra array(54) can be added to prevent shifting error when the amounts of shifting and the number of input are not the same.
Abstract translation: 目的：提供基于左移位结构的移位器，以防止当偏移量和左右移位的输入数不相同时发生错误。 构成：基于左移结构的移位器（100）包括输入缓冲器（20），MASK解码器（30），MASK发生器（40），移位阵列（50），输出缓冲器（60），刻度 元素解码器（70）和选项解码器（50）。 这里，移位阵列（50）仅具有左移位的结构。 而在所有其他操作（如MASK生成）完成后，都会发生移位。 MASK生成器（40）在移位后形成填充剩余位的模式。 选择解码器（80）解码用于在由MASK生成器（40）形成的图案中进行选择的控制信号。 并且当移位量和输入数量不相同时，可以添加额外的数组（54）以防止移位错误。
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公开(公告)号：KR1020010019861A
公开(公告)日：2001-03-15
申请号：KR1019990036515
申请日：1999-08-31
Applicant: 삼성전자주식회사
IPC: G06F7/50
Abstract: PURPOSE: A conditional selective adder is provided to enhance an operation speed, reduce a current consumption by a level restore and a time delay block by selectiveing a pre-calculated sum based on a carry bit. CONSTITUTION: The unit comprises eight 8 bit conditional selective addition modules(10-80). Each 8 bit conditional selective addition modules(10-80) includes a PGB(Pre carry & sum Generation Block), a SGB(Sum Generation Block), and a CGB(Carry Generation Block). The carries generated from each 8 bit conditional selective addition modules(10-80) are all input into a BCGB(Block Carry Generation Block). The PGB(12) analyzes input values to be added at a first conditional selective addition module(10), and outputs a proper value in advance. At this time, the SGB(14) generates a sum in the case that a carry exists, and a sum in the case that a carry does not exist. The CGB(16) transmits the carry of the first conditional selective addition module(10) to the BCGB(90). At this time, the PGBs included in the remaining conditional selective addition modules(20-80) analyzes the input values to be added at the remaining conditional selective addition modules(20-80), and each SGBs generates a sum in the case that a carry exists, and a sum in the case that a carry does not exist.
Abstract translation: 目的：提供一种条件选择加法器，以通过基于进位位选择预先计算的总和来提高操作速度，通过电平恢复和时间延迟块来减少电流消耗。 规定：该单元包括8个8位条件选择加法模块（10-80）。 每个8位条件选择性附加模块（10-80）包括PGB（预进位和和产生块），SGB（Sum生成块）和CGB（进位产生块）。 从每个8位条件选择加法模块（10-80）产生的载波都被输入到BCGB（块进位产生块）中。 PGB（12）分析在第一条件选择加法模块（10）中添加的输入值，并且预先输出适当的值。 此时，SGB（14）在进位存在的情况下产生和，而在进位不存在的情况下，产生和。 CGB（16）将第一条件选择加法模块（10）的进位传送到BCGB（90）。 此时，包含在剩余的条件选择加法模块（20-80）中的PGB分析在剩余的条件选择加法模块（20-80）下要添加的输入值，并且每个SGB在以下情况下产生和： 携带存在，并且在进位不存在的情况下的总和。
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公开(公告)号：KR100224278B1
公开(公告)日：1999-10-15
申请号：KR1019960067478
申请日：1996-12-18
Applicant: 삼성전자주식회사
Inventor： 송민규
IPC: H03K19/00
CPC classification number: G06F7/5318 , G06F7/507 , G06F2207/4816
Abstract: 여기에 개시되는 집적화된 패스 트랜지스터 로직 회로는 7개의 모듈화된 합 발생 블록들과, 2개의 캐리 발생 블록들로 구성되는 조건 합 가산기를 구비한다. 상기 조건 합 가산기에서, 각 합 발생 블록들 내에 존재하는 멀티플렉서 체인을 통한 캐리 전파가 상기 체인의 최종 단에 도달하기 전에 상기 최종 단은 각 캐리 발생 블록들로부터의 블록 캐리 (BC
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