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公开(公告)号：KR1020130111841A
公开(公告)日：2013-10-11
申请号：KR1020120034044
申请日：2012-04-02
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/49827 , H01L21/768 , H01L23/3192 , H01L23/49811 , H01L23/5226 , H01L24/05 , H01L24/13 , H01L2224/02125 , H01L2224/0214 , H01L2224/02145 , H01L2224/0401 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/13021 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2224/81424 , H01L2224/81447 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2224/05552
Abstract: PURPOSE: A semiconductor package is provided to obtain a stable package by forming first circuit patterns which form a line and space shape. CONSTITUTION: A circuit substrate (170) includes a substrate pad (175). A semiconductor chip (100) includes a chip pad (140). A connection pattern electrically connects the circuit substrate and the semiconductor chip. The semiconductor chip comprises a first via. The chip pad includes a first region and a second region.
Abstract translation: 目的：提供半导体封装以通过形成形成线和空间形状的第一电路图案来获得稳定的封装。 构成：电路衬底（170）包括衬底（175）。 半导体芯片（100）包括芯片焊盘（140）。 连接图案电连接电路基板和半导体芯片。 半导体芯片包括第一通孔。 芯片焊盘包括第一区域和第二区域。
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公开(公告)号：KR1020170057920A
公开(公告)日：2017-05-26
申请号：KR1020150161302
申请日：2015-11-17
Applicant: 삼성전자주식회사
CPC classification number: H01L23/562 , H01L21/561 , H01L21/565 , H01L23/13 , H01L23/3121 , H01L24/13 , H01L24/16 , H01L24/97 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/97 , H01L2924/15151 , H01L2924/181 , H01L2924/3512 , H01L2924/00012 , H01L2224/81 , H01L2924/014 , H01L2924/00014
Abstract: 본발명의개념에따른상면에실장된반도체칩들로몰딩수지가공급되어몰딩공정이수행되는인쇄회로기판에있어서, 상기인쇄회로기판은상기반도체칩들이실장되는칩 영역들및 상기칩 영역들각각을둘러싸는스크라이브영역을포함하되, 상기몰딩수지는제 1 방향을따라공급되고, 상기스크라이브영역은상기제 1 방향을따라형성된제 1 벤트홀들을포함한다.
Abstract translation: 被供给到安装在根据本发明的印刷电路板进行成形处理的概念的顶表面上的半导体芯片的树脂模制品，该印刷电路板是每个芯片区域的安装在半导体芯片和芯片面积 其中模塑树脂沿第一方向供应，并且划线区域包括沿着第一方向形成的第一通气孔。
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公开(公告)号：KR1020150141440A
公开(公告)日：2015-12-18
申请号：KR1020140070164
申请日：2014-06-10
Applicant: 삼성전자주식회사
IPC: H01L23/13
CPC classification number: H01L25/0657 , H01L21/78 , H01L24/03 , H01L24/05 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/0233 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2225/06524 , H01L2225/06565 , H01L2924/1434 , H01L2924/1436 , H01L2924/1441 , H01L2224/03
Abstract: 예시적인실시예들에따른반도체패키지는복수개의접속패드들을갖는기판, 및기판상에적층되는제1 반도체칩을포함한다. 제1 반도체칩은제1 면및 제1 면에마주하는제2 면을갖는제1 반도체칩 바디, 제1 반도체칩 바디의제1 면상에배치되는제1 접속패드, 및제1 반도체칩 바디의제1 면상에배치되며제1 접속패드와전기적으로연결되고제1 반도체칩 바디의외측면까지연장되고요철구조를갖는일단부를갖는제1 재배선패드를포함할수 있다. 재배선패드는일단부에요철구조를가지므로도전라인으로기판의접속패드와재배선패드를연결할때 전기적연결신뢰성을높일수 있다.
Abstract translation: 根据本发明的示例性实施例，半导体封装包括：具有多个连接焊盘的衬底; 以及堆叠在所述基板上的第一半导体芯片。 第一半导体封装芯片包括：第一半导体芯片本体，具有第一表面和与第一表面相对的第二表面; 布置在第一半导体芯片主体的第一表面上的第一连接焊盘; 以及布置在所述第一半导体芯片主体的所述第一表面上的第一重新布线焊盘，其电连接到所述第一连接焊盘，并且具有以不均匀结构延伸到所述第一半导体芯片主体的外表面的一个端部单元。 由于重新布线板在一端单元中具有不均匀的结构，所以当用导线连接基板的连接垫和再布线垫时，可以提高电连接的可靠性。
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公开(公告)号：KR1020140049199A
公开(公告)日：2014-04-25
申请号：KR1020120115036
申请日：2012-10-16
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49838 , H01L23/49811 , H01L25/0652 , H01L25/0657 , H01L2224/16145 , H01L2224/32145 , H01L2224/48227 , H01L2224/73207 , H01L2224/81193 , H01L2225/0651 , H01L2225/06513 , H01L2924/15311
Abstract: A semiconductor package is provided. The semiconductor package according to an embodiment of the present invention, includes a lower semiconductor chip; and an upper semiconductor chip which is flip-chip-bonded to the lower semiconductor chip. The lower and the upper semiconductor chip include a first bonding pad which is formed on an active surface where a center line extended in a first direction is defined, and a first redistribution line which includes a first and a second connection region which are electrically connected to the first bonding pad and are arranged in an opposite direction with the same distance from the center line in a second direction vertical to the first direction.
Abstract translation: 提供半导体封装。 根据本发明的实施例的半导体封装包括下半导体芯片; 以及将下半导体芯片倒装芯片接合的上半导体芯片。 下半导体芯片和上半导体芯片包括形成在沿着第一方向延伸的中心线的有源表面上的第一焊盘，以及包括第一和第二连接区域的第一再分配线，该第一和第二连接区域电连接到 所述第一焊盘并且在与所述第一方向垂直的第二方向上以与所述中心线相同的距离的相反方向布置。
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Patent Agency Ranking
公开(公告)号：KR1020130109791A
公开(公告)日：2013-10-08
申请号：KR1020120031825
申请日：2012-03-28
Applicant: 삼성전자주식회사
CPC classification number: H01L24/46 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/05553 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/45664 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package is inexpensively produced in large quantities and has a low loading factor. CONSTITUTION: A semiconductor package includes a master chip (120) and a slave chip (130a) laminated on a substrate (110). The master chip and the slave chip are connected in series for an external circuit. The master chip and the slave chip are connected through a bonding wire. The master chip includes a control circuit controlling the input and output of data and a signal for the slave chip. The footprint of the master chip is substantially same as the footprint of the slave chip. [Reference numerals] (110) Substrate; (120) Master chip; (130a) Slave chip
Abstract translation: 目的：半导体封装大量生产成本低，负载率低。 构成：半导体封装包括层叠在基板（110）上的主芯片（120）和从芯片（130a）。 主芯片和从芯片串联连接外部电路。 主芯片和从芯片通过接合线连接。 主芯片包括控制数据的输入和输出以及从芯片的信号的控制电路。 主芯片的占用面积与从芯片的占用面积基本相同。 （附图标记）（110）基板; （120）主芯片; （130a）从芯片
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公开(公告)号：KR101916088B1
公开(公告)日：2018-11-07
申请号：KR1020120034044
申请日：2012-04-02
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/49827 , H01L21/768 , H01L23/3192 , H01L23/49811 , H01L23/5226 , H01L24/05 , H01L24/13 , H01L2224/02125 , H01L2224/0214 , H01L2224/02145 , H01L2224/0401 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/13021 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2224/81424 , H01L2224/81447 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2224/05552
Abstract: 반도체패키지를제공한다. 반도체패키지는, 기판패드를포함하는회로기판, 회로기판과마주하며이격되어배치되며, 칩패드를포함하는반도체칩 및회로기판및 반도체칩을전기적으로연결하는연결패턴을포함한다. 반도체칩은, 상기반도체칩 내에, 반도체칩의상면에대하여수직하게배치되는다수의제1 회로패턴들과, 칩패드및 제1 회로패턴들을전기적으로연결하는제1 비아를포함한다. 칩패드는, 연결패턴이접촉되는제1 영역및 제1 영역의외각의제2 영역을포함하되, 제1 비아는상기제2 영역에연결된다.
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公开(公告)号：KR101898678B1
公开(公告)日：2018-09-13
申请号：KR1020120031825
申请日：2012-03-28
Applicant: 삼성전자주식회사
CPC classification number: H01L24/46 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/05553 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/45664 , H01L2924/00012
Abstract: 본발명은반도체패키지에관한것으로서, 더욱구체적으로기판상에적층된마스터칩 및슬레이브칩을포함하는반도체패키지로서, 상기마스터칩과슬레이브칩이외부회로에대하여직렬적으로연결되고, 상기마스터칩과상기슬레이브칩이본딩와이어를통하여연결된반도체패키지에관한것이다. 본발명의반도체패키지를이용하면낮은로딩팩터를갖는우수한성능의반도체패키지를저렴하게대량생산할수 있다.
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公开(公告)号：KR1020160128796A
公开(公告)日：2016-11-08
申请号：KR1020150060724
申请日：2015-04-29
Applicant: 삼성전자주식회사
CPC classification number: H01L43/08 , H01L23/049 , H01L23/051 , H01L23/055 , H01L23/06 , H01L23/10 , H01L23/14 , H01L23/293 , H01L23/3128 , H01L23/3142 , H01L23/552 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L43/12 , H01L2224/16227 , H01L2224/32245 , H01L2224/48091 , H01L2224/48108 , H01L2224/48245 , H01L2224/4912 , H01L2224/73265 , H01L2924/00014 , H01L2924/1443 , H01L2924/15311 , H01L2924/1815 , H01L2924/3025 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/48227 , H01L2924/00012
Abstract: 본발명의자기저항칩 패키지는회로기판과, 상기회로기판상에위치하는쉴딩베이스부및 상기쉴딩베이스부의일측에서연장된쉴딩중간부를포함하는쉴딩바디부와, 상기쉴딩베이스부상에위치하고, 자기저항셀 어레이를포함하는자기저항칩과, 상기자기저항칩과상기회로기판을전기적으로연결하는내부연결부와, 상기회로기판상에서상기자기저항칩을밀봉하고, 상기자기저항칩의상면보다높은상면을갖는밀봉부와, 상기쉴딩중간부, 밀봉부및 상기자기저항셀 어레이의상부에위치하는쉴딩덮개부를포함한다.
Abstract translation: 在一个实施例中，磁阻芯片封装包括电路板; 屏蔽体，其包括位于所述电路板上的屏蔽基部和从所述屏蔽基部的一侧延伸的屏蔽中间部; 位于所述屏蔽基底部分上并包括磁阻单元阵列的磁阻芯片; 将所述磁阻芯片电连接到所述电路板的内部连接部分; 封装部，将所述磁阻芯片封装在所述电路板上，并且具有比所述磁阻芯片的上表面高的上表面; 以及位于屏蔽中间部分上以及封装部分上的屏蔽罩。
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公开(公告)号：KR1020140008551A
公开(公告)日：2014-01-22
申请号：KR1020120073430
申请日：2012-07-05
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: H01L23/49816 , H01L21/561 , H01L21/565 , H01L23/13 , H01L23/49838 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48227 , H01L2224/49171 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/81193 , H01L2224/81194 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/15151 , H01L2924/15159 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/05552
Abstract: The present invention relates to a semiconductor package and a method of forming the same. According to the embodiment of the present invention, the semiconductor package includes a package substrate including at least one hole; a first semiconductor chip; a second semiconductor chip; and a molding layer formed on the package substrate. Bumps are formed between the first semiconductor chip and the second semiconductor chip.
Abstract translation: 本发明涉及一种半导体封装及其制造方法。 根据本发明的实施例，半导体封装包括包括至少一个孔的封装衬底; 第一半导体芯片; 第二半导体芯片; 以及形成在所述封装基板上的模制层。 在第一半导体芯片和第二半导体芯片之间形成有凸起。
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