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公开(公告)号：KR101638410B1
公开(公告)日：2016-07-11
申请号：KR1020090087069
申请日：2009-09-15
Applicant: 삼성전자주식회사
Abstract: 화상형성장치가개시된다. 본화상형성장치는, 화상형성잡 수행에사용되는엔진부, 엔진부의동작을제어하는엔진제어부, 엔진부를기동시키는복수의 BLDC 모터, 엔진제어부로부터복수의 BLDC 모터에대한디지털제어명령을수신하는통신인터페이스부, 복수의 BLDC 모터의구동정보를감지하는센서부, 복수의 BLDC 모터를제어하기위한구동신호를생성하는구동신호부, 및, 수신된디지털제어명령및 센서부의감지결과에따라구동신호부의동작을제어하는속도제어부를포함한다.
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公开(公告)号：KR1020140146880A
公开(公告)日：2014-12-29
申请号：KR1020130069754
申请日：2013-06-18
Applicant: 삼성전자주식회사
IPC: H01L23/367 , H01L23/373
CPC classification number: H01L23/34 , H01L23/3677 , H01L23/481 , H01L23/49811 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73253 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2224/48247 , H01L2924/00012 , H01L2924/00
Abstract: A semiconductor package according to an embodiment of the present invention includes: a lower package which includes a lower semiconductor chip mounted on a lower package substrate; an upper package which is stacked on the lower package and includes an upper semiconductor chip mounted on an upper package substrate which includes a center part adjacent to the lower semiconductor chip and an edge part; and a thermal boundary material which is filled between the lower package and the upper package to allow the upper package substrate to touch the upper surface of the lower semiconductor chip. The upper package substrate includes a thermal diffusion via which penetrates the center part of the upper package substrate and a connection via which is separated from the thermal diffusion via and penetrates the edge part of the upper package substrate.
Abstract translation: 根据本发明的实施例的半导体封装包括：下封装，其包括安装在下封装基板上的下半导体芯片; 堆叠在下封装上并包括安装在上封装基板上的上半导体芯片的上封装，该上封装基板包括与下半导体芯片相邻的中心部分和边缘部分; 以及填充在下封装和上封装之间的热边界材料，以允许上封装基板接触下半导体芯片的上表面。 上封装衬底包括穿过上封装衬底的中心部分的热扩散，以及与热扩散通道分离并穿透上封装衬底的边缘部分的连接。
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公开(公告)号：KR1020130090209A
公开(公告)日：2013-08-13
申请号：KR1020120011354
申请日：2012-02-03
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/30625 , B24C1/08 , H01L21/02021 , H01L21/02057 , H01L21/465 , H01L21/67219
Abstract: PURPOSE: An apparatus and method for processing a substrate are provided to easily remove foreign materials by spraying fluid on the substrate to perform a jet-polishing process. CONSTITUTION: A substrate is supported (S1210). Fluid is sprayed on the substrate (S1230). The fluid includes an abrasive. The substrate is jet-polished by the fluid (S1240). The fluid is sprayed on the non-pattern surface of the substrate. [Reference numerals] (AA) Start; (BB) Finish; (S1210) Support a substrate; (S1220) Supply fluid; (S1230) Jet-spray fluid; (S1240) Jet-spray a substrate
Abstract translation: 目的：提供一种用于处理基板的装置和方法，用于通过在基板上喷涂流体来简单地去除外来物质，进行喷射抛光处理。 构成：支撑基板（S1210）。 将流体喷涂在基板上（S1230）。 流体包括磨料。 基板被流体喷射抛光（S1240）。 将流体喷涂在基材的非图案表面上。 （附图标记）（AA）开始; （BB）完成; （S1210）支撑基板; （S1220）供液; （S1230）喷射流体; （S1240）喷射基板
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公开(公告)号：KR1020110029407A
公开(公告)日：2011-03-23
申请号：KR1020090087069
申请日：2009-09-15
Applicant: 삼성전자주식회사
Abstract: PURPOSE: An image forming apparatus, a motor controlling apparatus and a method for controlling thereof are provided to efficiently drive a plurality of BLDC motors. CONSTITUTION: An image forming apparatus, a motor controlling apparatus and a method for controlling thereof comprises: an engine unit, an engine controller; a plurality of BLDC motor driving the engine unit; a communication interface(100) receiving a digital control command of the plural BLDC motor; a sensor sensing the operation of the BLDC motor; a drive signal generator; and a speed controller controlling the operation of the drive signal generator based on a sensed result.
Abstract translation: 目的：提供一种图像形成装置，电动机控制装置及其控制方法，以有效地驱动多个BLDC电动机。 构成：图像形成装置，电动机控制装置及其控制方法包括：发动机单元，发动机控制器; 驱动发动机单元的多个BLDC电动机; 接收所述多个BLDC电动机的数字控制命令的通信接口（100） 感测BLDC电动机的操作的传感器; 驱动信号发生器; 以及速度控制器，其基于感测结果控制所述驱动信号发生器的操作。
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公开(公告)号：KR1020100063997A
公开(公告)日：2010-06-14
申请号：KR1020080122392
申请日：2008-12-04
Applicant: 삼성전자주식회사
Inventor： 신성호
CPC classification number: G02B26/127 , G02B26/085 , G02B26/105 , H04N1/053 , H04N1/1135 , H04N1/12 , H04N2201/02439 , H04N2201/0468 , H04N2201/0471 , H04N2201/04732 , H04N2201/04744 , H04N2201/04748 , H04N2201/04755 , H04N2201/04794
Abstract: PURPOSE: An optical scanning apparatus and a scan synchronization signal detecting method are provided to detect the scan synchronization signal with sensing current information flowing in a driver for driving a bias mirror. CONSTITUTION: A bias mirror(15) biases a beam irradiated from a light source to an exposure face. A photo sensor(20) is arranged on one side of a beam scan area by the bias mirror and detects the beam reflected from the bias mirror. A driving unit(35) drives the bias mirror. A sensing unit detects current information flowing in the driving unit.
Abstract translation: 目的：提供一种光学扫描装置和扫描同步信号检测方法，用于检测在用于驱动偏光镜的驱动器中流动的感测电流信息的扫描同步信号。 构成：偏光镜（15）将从光源照射的光束偏压到曝光面。 光传感器（20）通过偏置反射镜布置在光束扫描区域的一侧，并检测从偏光镜反射的光束。 驱动单元（35）驱动偏置镜。 感测单元检测在驱动单元中流动的当前信息。
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Patent Agency Ranking
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公开(公告)号：KR1020130109791A
公开(公告)日：2013-10-08
申请号：KR1020120031825
申请日：2012-03-28
Applicant: 삼성전자주식회사
CPC classification number: H01L24/46 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/05553 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/45664 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package is inexpensively produced in large quantities and has a low loading factor. CONSTITUTION: A semiconductor package includes a master chip (120) and a slave chip (130a) laminated on a substrate (110). The master chip and the slave chip are connected in series for an external circuit. The master chip and the slave chip are connected through a bonding wire. The master chip includes a control circuit controlling the input and output of data and a signal for the slave chip. The footprint of the master chip is substantially same as the footprint of the slave chip. [Reference numerals] (110) Substrate; (120) Master chip; (130a) Slave chip
Abstract translation: 目的：半导体封装大量生产成本低，负载率低。 构成：半导体封装包括层叠在基板（110）上的主芯片（120）和从芯片（130a）。 主芯片和从芯片串联连接外部电路。 主芯片和从芯片通过接合线连接。 主芯片包括控制数据的输入和输出以及从芯片的信号的控制电路。 主芯片的占用面积与从芯片的占用面积基本相同。 （附图标记）（110）基板; （120）主芯片; （130a）从芯片
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公开(公告)号：KR1020090016225A
公开(公告)日：2009-02-13
申请号：KR1020070080717
申请日：2007-08-10
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/762 , B24B9/065 , H01L21/3212
Abstract: A method for fabricating a semiconductor device is provided to prevent bad connection due to a corner by removing the corner protruded from a substrate. In a method for fabricating a semiconductor device, a first substrate and a second substrate are prepared. A side vertical to the surface of the second substrate is formed at the corner(106) of the second substrate. At this time, the corner protruded to the side direction of the second substrate is removed through etching. A defect layer(110) is formed inside of the second substrate which is adhered on the first substrate. A part of the second substrate is separated from the boundary of the defect layer.
Abstract translation: 提供了一种用于制造半导体器件的方法，以通过去除从基板突出的角部来防止由于拐角而造成的连接不良。 在制造半导体器件的方法中，准备第一衬底和第二衬底。 在第二基板的角部（106）处形成垂直于第二基板的表面的一侧。 此时，通过蚀刻去除突出到第二基板的侧面方向的角部。 在粘附在第一基板上的第二基板的内部形成缺陷层（110）。 第二衬底的一部分与缺陷层的边界分离。
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公开(公告)号：KR1020080069477A
公开(公告)日：2008-07-28
申请号：KR1020070007244
申请日：2007-01-23
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: G03F9/708 , H01L23/544 , H01L2223/54426 , H01L2223/5446
Abstract: A method for forming an align key is provided to prevent damage to align key groves and remove the asymmetry of an align mark by forming sacrificial layer patterns in align key grooves. A method for forming an align key comprises the steps of: forming trenches(104) and align key grooves(102) on a substrate(100); depositing opaque conductive layers on an entire surface of the substrate wherein the trenches and align key grooves are formed; depositing sacrificial layers on the opaque conductive layers; separating the opaque conductive layers and the sacrificial layers by processing a CMP(Chemical Mechanical Polishing) process; and removing the sacrificial layers. The opaque conductive layers are metal or a metal oxidation layer.
Abstract translation: 提供一种用于形成对准键的方法，以通过在对准键槽中形成牺牲层图案来防止损坏对准键槽并消除对准标记的不对称性。 一种用于形成对准键的方法包括以下步骤：形成沟槽（104）并对准衬底（100）上的键槽（102）; 在衬底的整个表面上沉积不透明导电层，其中形成沟槽和对准键槽; 在不透明导电层上沉积牺牲层; 通过加工CMP（化学机械抛光）工艺来分离不透明导电层和牺牲层; 并去除牺牲层。 不透明导电层是金属或金属氧化层。
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公开(公告)号：KR100817090B1
公开(公告)日：2008-03-26
申请号：KR1020070020576
申请日：2007-02-28
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/7688 , Y10S438/947
Abstract: A method for fabricating a semiconductor device is provided to form high-density second contact plugs of fine patterns by using first contact mask layers and second contact mask layers self-aligned with the first contact mask layers. An interlayer dielectric(110) is formed on a semiconductor substrate(105) in which first and second regions are confined. First contact plugs(115c) are formed on a part of the second region, filling a plurality of first contact holes penetrating the interlayer dielectric. A plurality of first contact mask layers(115a) are formed on the interlayer dielectric in the first region, and a plurality of first dummy mask layers(115b) are formed on the interlayer dielectric in the second region. A plurality of second contact mask layers(135a) are formed on the interlayer dielectric, disposed between adjacent two of the plurality of first contact mask layers. A plurality of second dummy mask layers(135b) are formed on the interlayer dielectric, disposed between adjacent two of the plurality of first dummy mask layers. By using as an etch protection layer the plurality of first contact mask layers and the plurality of second contact mask layers, the interlayer dielectric is etched to form a plurality of second contact holes penetrating the interlayer dielectric on the first region. The plurality of first contact mask layer and the plurality of first dummy mask layers can be formed simultaneously.
Abstract translation: 提供一种制造半导体器件的方法，通过使用与第一接触掩模层自对准的第一接触掩模层和第二接触掩模层来形成精细图案的高密度第二接触塞。 在第一和第二区域被限制的半导体衬底（105）上形成层间电介质（110）。 第一接触塞（115c）形成在第二区域的一部分上，填充穿过层间电介质的多个第一接触孔。 在第一区域中的层间电介质上形成多个第一接触掩模层（115a），并且在第二区域中的层间电介质上形成多个第一伪掩模层（115b）。 多个第二接触掩模层（135a）形成在层间电介质上，设置在多个第一接触掩模层的相邻两个之间。 多个第二虚设掩模层（135b）形成在层间电介质上，设置在多个第一伪掩模层中相邻的两个之间。 通过使用多个第一接触掩模层和多个第二接触掩模层作为蚀刻保护层，蚀刻层间电介质以形成穿过第一区域上的层间电介质的多个第二接触孔。 多个第一接触掩模层和多个第一伪掩模层可以同时形成。
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