公开(公告)号：KR101435519B1

公开(公告)日：2014-08-29

申请号：KR1020080072438

申请日：2008-07-24

Applicant: 삼성전자주식회사

Inventor： 차대길 ,  진영구 ,  민복기 ,  박윤동

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  B82Y20/00 ,  B82Y30/00 ,  H01L27/14625

Abstract: 광 포커싱 구조를 가진 이미지 센서에 관하여 개시된다. 개시된 광 포커싱 구조를 가진 이미지 센서는 광전변환영역에 입사되는 광을 상기 광전변환영역에 포커싱시키는 적어도 하나의 금속나노도트를 구비한다. 상기 금속 나노도트는 상기 광전변환영역 상에 배치되거나 또는 상기 광전변환영역의 상면에 노출되게 상기 광전변환영역에 임베드된다.

公开(公告)号：KR1020110033567A

公开(公告)日：2011-03-31

申请号：KR1020090091113

申请日：2009-09-25

Applicant: 삼성전자주식회사

Inventor： 황수정 ,  포썸,에릭알. ,  진영구 ,  박윤동 ,  차대길

IPC: H01L27/146

CPC classification number: H04N5/3696 ,  H01L27/14621 ,  H01L27/14645 ,  H04N5/2257 ,  H04N5/332

Abstract: PURPOSE: An image sensor having a depth sensor is provided to increase the recombination of electrons and holes by forming a potential barrier to preventing the movement of electronics generated from the depth region in the lower part of a substrate. CONSTITUTION: In an image sensor having a depth sensor. A substrate(101) comprises a visible light recognition domain(I) and a non-visible light recognition domain(II). A first well(123a) and a second well(123b) of a first conductive type are formed in the non-visible light recognition domain. A first gate(122a) and a second gate(122b) apply voltage to the first well and the second well respectively. A photoelectric conversion element(110R,110G) is formed between the first gate and the second gate. The photoelectric conversion element comprises pinning layers(112R,112G) formed in the upper part of the substrate.

Abstract translation: 目的：提供具有深度传感器的图像传感器，以通过形成势垒来增加电子和空穴的复合，以防止从衬底下部的深度区域产生的电子元件的移动。 构成：在具有深度传感器的图像传感器中。 基板（101）包括可见光识别域（I）和不可见光识别域（II）。 第一导电类型的第一阱（123a）和第二阱（123b）形成在不可见光识别域中。 第一栅极（122a）和第二栅极（122b）分别向第一阱和第二阱施加电压。 光电转换元件（110R，110G）形成在第一栅极和第二栅极之间。 光电转换元件包括形成在基板上部的钉扎层（112R，112G）。

公开(公告)号：KR1020100031401A

公开(公告)日：2010-03-22

申请号：KR1020080090489

申请日：2008-09-12

Applicant: 삼성전자주식회사

Inventor： 김원주 ,  이태희 ,  박윤동 ,  최상무 ,  차대길

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/0688 ,  H01L27/108 ,  H01L27/10882

Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to reduce the number of process steps for manufacturing a multi-layered semiconductor device to be identical to the number of process steps for manufacturing a single layer semiconductor device. CONSTITUTION: First active regions(211, 212, 213) second active regions(221, 222, 223) and third active regions(231, 232, 233) are successively arranged. The second active regions are arranged in an upper layer than a layer in which the first active regions are arranged. The third active regions are arranged in an upper layer than the layer in which the second active regions are arranged. The active regions are expanded to an identical direction with a pre-set gap and are parallelly arranged. Impurity doping regions are formed along the both edge of the active regions.

Abstract translation: 目的：提供半导体器件及其制造方法，以减少用于制造多层半导体器件的工艺步骤的数量与制造单层半导体器件的工艺步骤的数量相同。 构成：连续布置第一有源区（211,212,213）第二有源区（221,222,223）和第三有源区（231,232,233）。 第二有源区域布置在比布置有第一有源区域的层的上层中。 第三有源区域布置在比设置第二有源区域的层的上层。 有源区域以预设的间隙扩展到相同的方向并且平行布置。 杂质掺杂区沿着有源区的两边形成。

公开(公告)号：KR1020090119461A

公开(公告)日：2009-11-19

申请号：KR1020080045521

申请日：2008-05-16

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 차대길 ,  신중훈 ,  박윤동 ,  진영구 ,  양문승 ,  조인성 ,  장지수

IPC: G02B6/13 ,  B82Y30/00

CPC classification number: H01S3/0632 ,  H01S3/0637 ,  H01S3/0933 ,  H01S3/09403 ,  H01S3/1608 ,  H01S3/1691

Abstract: PURPOSE: An optical amplifying medium, a manufacturing method thereof, and an optical device including the optical amplifying medium are provided to used as an optical inter connector between chips by being easily applied to an existing semiconductor device. CONSTITUTION: A first material layer and a second material layer are formed on a substrate(100). The first material layer(10) dopes an activator. The second material layer(20) includes a sensitizer. The activator is erbium. The sensitizer is silicon nano cluster. The substrate is annealed in order to form the sensitizer inside the second material layer.

Abstract translation: 目的：提供一种光放大介质及其制造方法以及包括该光放大介质的光学器件，以容易地应用于现有的半导体器件，作为芯片间的光学连接器。 构成：在基板（100）上形成第一材料层和第二材料层。 第一材料层（10）涂覆活化剂。 第二材料层（20）包括敏化剂。 活化剂是铒。 敏化剂是硅纳米簇。 为了在第二材料层内部形成敏化剂，将基板退火。

公开(公告)号：KR101497542B1

公开(公告)日：2015-03-02

申请号：KR1020080103201

申请日：2008-10-21

Applicant: 삼성전자주식회사

Inventor： 최상무 ,  김원주 ,  이태희 ,  차대길

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C2207/2227 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10844 ,  H01L29/7841

Abstract: 반도체 소자의 동작 방법이 개시된다. 본 발명의 실시예에 따른 반도체 소자의 동작 방법은, 전압 펄스의 타이밍을 조절하여 동작 모드를 설정하거나 또는 전압 펄스의 전압 레벨을 조절하여 동작 모드를 설정한다.

公开(公告)号：KR1020100112878A

公开(公告)日：2010-10-20

申请号：KR1020090031396

申请日：2009-04-10

Applicant: 삼성전자주식회사

Inventor： 차대길 ,  포썸,에릭알. ,  진영구 ,  박윤동 ,  황수정

IPC: H01L27/146

CPC classification number: H01L31/112 ,  H01L27/14609 ,  H04N5/335 ,  H04N5/374

Abstract: PURPOSE: An image sensor with high sensitivity is provided to obtain a high conversion gain by functioning as a photoelectric conversion device and a sensing device through a single electron field effect transistor. CONSTITUTION: An n type well(210) is formed on a p type sub substrate. A source region(220) and a drain region(230) are formed on the n type well. A channel region(250) connects the source region to the drain region. A gate region(240) is formed on the lower side of the channel region. The n type well is an impurity region doped with lower density than the gate region.

Abstract translation: 目的：提供高灵敏度的图像传感器，通过用作光电转换装置和通过单电子场效应晶体管的感测装置来获得高转换增益。 构成：在p型副基板上形成n型阱（210）。 源极区（220）和漏极区（230）形成在n型阱上。 沟道区域（250）将源极区域连接到漏极区域。 栅极区域（240）形成在沟道区域的下侧。 n型阱是掺杂比栅极区更低密度的杂质区。

公开(公告)号：KR1020100043936A

公开(公告)日：2010-04-29

申请号：KR1020080103201

申请日：2008-10-21

Applicant: 삼성전자주식회사

Inventor： 최상무 ,  김원주 ,  이태희 ,  차대길

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C2207/2227 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10844 ,  H01L29/7841

Abstract: PURPOSE: An operation method of a semiconductor device are provided to divide an erase mode and an input mode by controlling timing and a voltage level of voltage pulse. CONSTITUTION: A data state of a semiconductor device is changed into a first state in an erase mode. In the erase mode, a gate voltage pulse is transited from an enable state to a standby state after a drain voltage, supplied to a gate region(130), is transited from an enable state to a standby state. The data state of a conductive device is changed a second state in a write mode. In the write mode, a gate voltage pulse is transited from an enable state to a standby state, and then a drain voltage is transited from an enable state to a standby state.

Abstract translation: 目的：提供一种半导体器件的操作方法，通过控制电压脉冲的定时和电压电平来分频擦除模式和输入模式。 构成：以擦除模式将半导体器件的数据状态改变为第一状态。 在擦除模式中，在提供给栅极区域（130）的漏极电压从使能状态转移到待机状态之后，栅极电压脉冲从使能状态转移到待机状态。 导电装置的数据状态在写入模式下改变为第二状态。 在写入模式中，栅极电压脉冲从使能状态转移到待机状态，然后将漏极电压从使能状态转移到待机状态。

公开(公告)号：KR1020100018449A

公开(公告)日：2010-02-17

申请号：KR1020090051952

申请日：2009-06-11

Applicant: 삼성전자주식회사

Inventor： 이승훈 ,  박윤동 ,  진영구 ,  장승혁 ,  차대길

IPC: H01L27/146

CPC classification number: H01L27/14645 ,  H01L27/14641 ,  H04N5/332 ,  H04N5/3696 ,  H04N5/37457 ,  H04N13/229 ,  H04N13/257

Abstract: PURPOSE: A pixel array of three dimensional image sensor is provided to improve an image resolution or sensitivity by arranging a plurality of range finding pixels intimately and finding ranges respectively or integratedly according to illuminance. CONSTITUTION: A green pixel(G), a red pixel(R) and a range finding pixel(Z) are formed on a p-type substrate(120). The green pixel includes a micro lens(130), a green filter(131) and a photoelectric transformation element(132). The red pixel(R) includes a micro lens(140), a red filter(141) and a photoelectric transformation element(142). The photoelectric transformation elements(132,142) are n-type area and form a p-n junction photodiode with p-type substrate. The micro lenses are formed with the same size. The photoelectric transformation elements are formed with the same depth from the surface of the substrate.

Abstract translation: 目的：提供三维图像传感器的像素阵列，以通过紧密地布置多个测距像素并根据照度分别或综合地发现范围来改善图像分辨率或灵敏度。 构成：在p型基板（120）上形成绿色像素（G），红色像素（R）和测距像素（Z）。 绿色像素包括微透镜（130），绿色滤光器（131）和光电转换元件（132）。 红色像素（R）包括微透镜（140），红色滤光器（141）和光电转换元件（142）。 光电转换元件（132,142）是n型区域并形成具有p型衬底的p-n结光电二极管。 微透镜以相同的尺寸形成。 光电转换元件与衬底表面形成相同的深度。

公开(公告)号：KR1020090092678A

公开(公告)日：2009-09-01

申请号：KR1020080089998

申请日：2008-09-11

Applicant: 삼성전자주식회사

Inventor： 이태희 ,  김원주 ,  박윤동 ,  차대길

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7391 ,  G11C11/404 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/8618

Abstract: A semiconductor device and semiconductor apparatus are provided to prevent the first and the second impurity doping area from being overlapped by separating the gate pattern from the first and the second impurity doping area. The semiconductor device comprises the semiconductor substrate(310), the body region(370), gate patters(330a, 330b), the first impurity doping region(340) and the second impurity doping region(350). The body region is located on surface the semiconductor substrate. The gate pattern is arranged in both side of the body region. The first and the second impurity doping region are positioned on the upper part of the body region.

Abstract translation: 提供半导体器件和半导体器件，以通过将栅极图案与第一和第二杂质掺杂区域分离来防止第一和第二杂质掺杂区域重叠。 半导体器件包括半导体衬底（310），体区（370），栅极图案（330a，330b），第一杂质掺杂区域（340）和第二杂质掺杂区域（350）。 身体区域位于半导体衬底的表面上。 门图案布置在身体区域的两侧。 第一和第二杂质掺杂区域位于身体区域的上部。

公开(公告)号：KR1020090092103A

公开(公告)日：2009-08-31

申请号：KR1020080017419

申请日：2008-02-26

Applicant: 삼성전자주식회사

Inventor： 김원주 ,  이태희 ,  차대길 ,  박윤동

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L29/7841

Abstract: A semiconductor substrate and a method for manufacturing the semiconductor substrate are provided to form the body region from the bulk semiconductor substrate by selectively etching the center region of the bulk semiconductor substrate. A semiconductor substrate comprises a substrate region(110), a body region(150) and an insulating area(130). The insulating area is positioned on the substrate region. The body region is positioned on the insulating area while separated from the substrate region. A plurality of insulating layers is arranged between the body regions. A plurality of insulating layers separates the plurality of body regions. The insulating layers arranged between body regions are connected to the insulating area. The semiconductor substrate is formed from the bulk semiconductor substrate.

Abstract translation: 提供半导体衬底和制造半导体衬底的方法，以通过选择性地蚀刻体半导体衬底的中心区域从体半导体衬底形成体区。 半导体衬底包括衬底区域（110），体区域（150）和绝缘区域（130）。 绝缘区域位于基板区域上。 身体区域位于绝缘区域上，同时与衬底区域分离。 在身体区域之间布置有多个绝缘层。 多个绝缘层分离多个身体区域。 布置在主体区域之间的绝缘层连接到绝缘区域。 半导体衬底由体半导体衬底形成。