다중처리기 시스템에서의 데이타 전송방법
    11.
    发明授权
    다중처리기 시스템에서의 데이타 전송방법 失效
    多处理器中数据传输的方法

    公开(公告)号:KR1019930003993B1

    公开(公告)日:1993-05-19

    申请号:KR1019890019313

    申请日:1989-12-22

    Abstract: The method transmits data smoothly through data bus by monopolizing the bus only in memory consulting operation of a processor and the related memory. It comprises the three stages: in the 1st stage a processor drives a certain address on address bus during a certain period of a bus clock; in the 2nd stage the memory selected by the certain address stores the certain address during the certain bus clock; and in the 3rd stage when the process of storing is completed, the processor cancells the occupation of the address bus the make other processor use the address bus.

    Abstract translation: 该方法仅在处理器和相关存储器的存储器咨询操作中通过垄断总线通过数据总线平滑地传输数据。 它包括三个阶段:在第一阶段,一个处理器在总线时钟的一定时间段内在地址总线上驱动某个地址; 在第二阶段,特定地址选择的存储器在特定的总线时钟存储特定地址; 并且在存储过程完成的第三阶段中,处理器取消对其他处理器使用地址总线的占用地址总线。

    컴퓨터 한의진단 처리의 속도향상 방식
    17.
    发明授权
    컴퓨터 한의진단 처리의 속도향상 방식 失效
    韩国医学诊断系统

    公开(公告)号:KR1019910009099B1

    公开(公告)日:1991-10-28

    申请号:KR1019870011569

    申请日:1987-10-19

    Abstract: The method is for improving the inference part of the Chinese diagnosis process. The predicate membership table (PMT;16) is stored in a memory (10) which corresponding column is searched by a PMT searcher (21b) so that the diagnosis speed is increased. The method only uses the hypothesis generation type knowledge (HG-type;13), hypothesis confirmation type knowledge (HC-type;14), regulation number of definition type knowledge, clinical parameter name, clinical parameter value, condition, and result to reduce the diagnosis process so that the logical process is performed small memory capacity.

    Abstract translation: 该方法是改进中国诊断过程的推理部分。 谓词隶属关系表(PMT; 16)被存储在存储器(10)中,由PMT搜索器(21b)搜索相应的列,从而提高诊断速度。 该方法仅使用假设生成类型知识(HG型; 13),假设确认类型知识(HC型; 14),定义类型知识的调节数,临床参数名称,临床参数值,条件和结果减少 诊断过程使逻辑过程执行小容量。

    다중처리기의 버스상태분석기
    20.
    发明授权
    다중처리기의 버스상태분석기 失效
    用于多处理器系统的总线状态分析器

    公开(公告)号:KR1019930007019B1

    公开(公告)日:1993-07-26

    申请号:KR1019900021857

    申请日:1990-12-26

    Abstract: The bus state analyzer debugs a multiprocessor system which adapts synchronous pended transmission type. The bus state analyzer includes a bus timing control signal generator (2) for generating timing control signal of buses, a bus interface unit (1) for receiving data from system bus according to timing control signal, a bus data search unit (3) for comparing bus data of the bus interface unit (1) and internal bus data, a function controller (4) for generating bus control signal according to bus clock signal and data coincide signal transmitted from the bus data search unit (3), a data memory (5) for storing input data of the bus interface unit on a data area which is determined by a control signal transmitted from the function controller, and processor unit (6) for controlling analyzing process.

    Abstract translation: 总线状态分析器调试适应同步倾斜传输类型的多处理器系统。 总线状态分析器包括用于产生总线定时控制信号的总线定时控制信号发生器(2),用于根据定时控制信号从系统总线接收数据的总线接口单元(1),总线数据搜索单元 比较总线接口单元(1)和内部总线数据的总线数据,根据总线时钟信号和从总线数据搜索单元(3)发送的数据重合信号产生总线控制信号的功能控制器(4),数据存储器 (5),用于将总线接口单元的输入数据存储在由功能控制器发送的控制信号确定的数据区域上,以及用于控制分析处理的处理器单元(6)。

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