中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

40 records (took 0.019 seconds)

    인터럽트 버스의 동기방법
    11.
    发明授权
    인터럽트 버스의 동기방법 失效
    中断总线同步方法

    公开(公告)号：KR1019920001815B1

    公开(公告)日：1992-03-03

    申请号：KR1019890019309

    申请日：1989-12-22

    Applicant: 한국전자통신연구원

    Inventor： 박병관 ,  강경용 ,  심원세 ,  기안도 ,  윤남석 ,  윤용호 ,  권오건 ,  박승규

    IPC: G06F13/24

    Abstract: checking whether there is an interrupt transmission request from one of processors (1) and (2) to an interrupt requestor (4); checking whether an interrupt bus synchronizing signal is true; waiting until the interrupt bus synchronizing signal becomes false by being fed-back if the signal is true; issuing a use request for the interrupt bus (3) if the signal is false; transmitting an interrupt to the interrupt bus (3) by utilizing one of interrupt processors (5) and (6); checking whether the transmission of the interrupt has been completed; and terminating the interrupt transmission by inputting an interrupt synchronizing signal through a signal line (6b).

    Abstract translation: 检查处理器（1）和（2）之一是否存在到中断请求者（4）的中断传输请求; 检查中断总线同步信号是否为真; 如果信号为真，则等待中断总线同步信号通过反馈变为假; 如果信号为假，则发出中断总线（3）的使用请求; 通过利用中断处理器（5）和（6）之一向中断总线（3）发送中断; 检查中断的传输是否已经完成; 并通过信号线（6b）输入中断同步信号来终止中断发送。

    다중처리기 시스템에서의 데이터 전송 제어장치
    17.
    发明授权
    다중처리기 시스템에서의 데이터 전송 제어장치 失效
    多处理器系统中的数据传输控制装置

    公开(公告)号：KR1019920002663B1

    公开(公告)日：1992-03-31

    申请号：KR1019890019312

    申请日：1989-12-22

    Applicant: 한국전자통신연구원

    Inventor： 박병관 ,  강경용 ,  심원세 ,  기안도 ,  윤남석 ,  윤용호 ,  임기욱 ,  오길록

    IPC: G06F13/14

    Abstract: The apparatus includes a data transmission bus requestor (2) for carrying out data transmissions and for informing it to a processor (1). A responder (2) transfers the task to a memory (4), and informs the result to the data transmission bus requestor (2). An address region encoder (12) forms an address region in accordance with the output of the processor (1), and a parity generator (13) generates parity signals for data transmissions. A slot address translator (14) generates address tags, and a tag receiver (20) receives the address tags through the system bus (3). A comparator (21) compares the address tags with the data tags. The apparatus maximizes the utilization of the system bus.

    Abstract translation: 该装置包括用于执行数据传输并将其通知给处理器（1）的数据传输总线请求器（2）。 响应者（2）将任务传送到存储器（4），并将结果通知给数据传输总线请求者（2）。 地址区域编码器（12）根据处理器（1）的输出形成地址区域，并且奇偶生成器（13）产生用于数据传输的奇偶校验信号。 插槽地址转换器（14）产生地址标签，标签接收器（20）通过系统总线（3）接收地址标签。 比较器（21）将地址标签与数据标签进行比较。 该装置使系统总线的利用最大化。

Patent Agency Ranking