公开(公告)号：KR100789922B1

公开(公告)日：2008-01-02

申请号：KR1020060118985

申请日：2006-11-29

Applicant: 한국전자통신연구원

Inventor： 최철종 ,  장문규 ,  김약연 ,  김태엽 ,  전명심 ,  이성재

IPC: H01L21/24 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/0847 ,  H01L29/665

Abstract: A method for manufacturing a semiconductor device and a semiconductor device manufactured using the same are provided to form a semiconductor device to which a metal silicide is adopted without a space structure by forming a gate electrode with a conductive compound. A gate dielectric is formed on a substrate(10). A conductive compound, which is not reacted with a metal layer to be formed through a subsequent process, is formed on the gate dielectric. The conductive compound and the gate dielectric are etched to form a gate electrode(12A). The metal layer is formed on a top of the substrate including the gate electrode. The metal and silicon contained in the substrate are reacted to form a source and drain region(14) comprised of a metal silicide layer on the substrate exposed at both sides of the gate electrode. After forming the metal silicide layer, the remaining metal layer which is not reacted with the silicon is removed.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的半导体器件，以形成通过形成具有导电化合物的栅电极而不具有空间结构的金属硅化物的半导体器件。 在基板（10）上形成栅极电介质。 在栅极电介质上形成导电化合物，其不与通过后续工艺形成的金属层反应。 蚀刻导电化合物和栅极电介质以形成栅电极（12A）。 金属层形成在包括栅电极的基板的顶部上。 包含在基板中的金属和硅被反应以形成由栅极电极的两侧露出的基板上的金属硅化物层构成的源区和漏区（14）。 在形成金属硅化物层之后，除去未与硅反应的剩余金属层。

公开(公告)号：KR1020070059900A

公开(公告)日：2007-06-12

申请号：KR1020060074492

申请日：2006-08-08

Applicant: 한국전자통신연구원

Inventor： 전명심 ,  장문규 ,  김약연 ,  최철종 ,  박병철 ,  이성재

IPC: H01L21/335 ,  H01L29/872

Abstract: A schottky barrier tunnel transistor is provided to form a stable high-performance N-type schottky barrier tunnel transistor with a low schottky barrier with respect to electrons by forming a schottky junction on the (111) surface of a silicon by an anisotropic etch process. An insulation layer(20) is deposited on a substrate(10). A source/drain(30a,30b) is formed on the insulation layer. A channel(90) is formed between the source and the drain. A gate insulation layer(40) and a gate electrode(60) are sequentially formed on the channel. A sidewall insulation layer(50) is formed on both sidewalls of the gate insulation layer and the gate electrode. The interface of one of the source or drain and the channel has a (111) surface of silicon, and at least a part of the source/drain including the silicon (111) surface is silicidized by a predetermined metal material to be a schottky junction. The channel can be higher than the source/drain so that the interface has a slope.

Abstract translation: 提供肖特基势垒隧道晶体管，以通过各向异性蚀刻工艺在硅的（111）表面上形成肖特基结，形成相对于电子具有低肖特基势垒的稳定的高性能N型肖特基势垒隧道晶体管。 绝缘层（20）沉积在衬底（10）上。 源极/漏极（30a，30b）形成在绝缘层上。 在源极和漏极之间形成沟道（90）。 栅极绝缘层（40）和栅电极（60）依次形成在沟道上。 在栅极绝缘层和栅电极的两个侧壁上形成侧壁绝缘层（50）。 源极或漏极和沟道之一的界面具有硅的（111）表面，并且包括硅（111）表面的源极/漏极的至少一部分被预定的金属材料硅化为肖特基结 。 通道可以高于源极/漏极，以使界面具有斜率。

公开(公告)号：KR100699462B1

公开(公告)日：2007-03-28

申请号：KR1020050119010

申请日：2005-12-07

Applicant: 한국전자통신연구원

Inventor： 장문규 ,  이성재 ,  김약연 ,  최철종 ,  전명심

IPC: H01L29/812

CPC classification number: H01L29/458 ,  H01L29/517 ,  H01L29/66643

Abstract: A schottky barrier tunnel transistor and a method for manufacturing the same are provided to form silicide for manufacturing a device having a schottky barrier by performing an ion implantation process and a thermal process. A substrate(300) is prepared. An active silicon layer is formed on the substrate. A gate insulating layer(315) is formed on one region of the silicon layer. A gate electrode(320) is formed on the gate insulating layer. Ions are implanted into a source/drain region(330) of the silicon layer on which the gate insulating layer is not formed. A thermal process for the silicon layer containing the implanted ions is performed. A sidewall spacer is formed on sidewalls of the gate insulating layer and the gate electrode.

Abstract translation: 提供肖特基势垒隧道晶体管及其制造方法，以通过进行离子注入工艺和热处理来形成用于制造具有肖特基势垒的器件的硅化物。 制备基板（300）。 在衬底上形成有源硅层。 在硅层的一个区域上形成栅极绝缘层（315）。 栅电极（320）形成在栅极绝缘层上。 将离子注入到其中未形成栅极绝缘层的硅层的源极/漏极区域（330）中。 进行含有注入离子的硅层的热处理。 在栅极绝缘层和栅电极的侧壁上形成侧壁间隔物。

公开(公告)号：KR1020080051010A

公开(公告)日：2008-06-10

申请号：KR1020070094687

申请日：2007-09-18

Applicant: 한국전자통신연구원

Inventor： 김태엽 ,  전명심 ,  김약연 ,  장문규 ,  최철종 ,  이성재 ,  박병철

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L21/67063 ,  H01L29/42324 ,  H01L29/513

Abstract: A highly-integrated semiconductor memory device and a manufacturing method thereof are provided to correctly read data by suppressing a leakage current generated as the semiconductor memory device is highly integrated. A source/drain electrode(220A) are formed on a silicon substrate to form a schottky junction with a channel region(220B). A floating gate composed of plural silicon nanodots(260A) is formed on the substrate of the channel region. The silicon nanodot is made of a silicon compound as a basal body, and a gate dielectric layer(270) is formed on the floating gate. A tunneling dielectric layer(250) is formed between the substrate of the channel region and the floating gate, and a control gate(280) is formed on the floating gate.

Abstract translation: 提供了一种高度集成的半导体存储器件及其制造方法，以通过抑制半导体存储器件高集成度时产生的漏电流来正确读取数据。 源极/漏极（220A）形成在硅衬底上以与沟道区（220B）形成肖特基结。 在沟道区的基板上形成由多个硅纳米点（260A）构成的浮置栅极。 硅纳米棒由硅化合物作为基体，在浮栅上形成栅介质层（270）。 在沟道区的衬底和浮置栅极之间形成隧穿电介质层（250），并且在浮动栅极上形成控制栅极（280）。

公开(公告)号：KR1020080051009A

公开(公告)日：2008-06-10

申请号：KR1020070094686

申请日：2007-09-18

Applicant: 한국전자통신연구원

Inventor： 김태엽 ,  장문규 ,  이성재 ,  김약연 ,  최철종 ,  전명심

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/47

CPC classification number: H01L27/108 ,  H01L27/095 ,  H01L29/66257

Abstract: A semiconductor memory device and a driving method thereof are provided to store an electric charge in a channel region by using a schottky barrier formed at an interface between a channel region and a source/drain electrode. A gate(160) is formed over a channel region(130) of a silicon substrate(100). A source electrode(110) and a drain electrode(120) are formed on the silicon substrate to form a schottky junction with the channel region. An electric charge is stored in a schottky barrier formed between the source electrode and the drain electrode. The source electrode and the drain electrode are made of same or different metal silicide. A level of the schottky junction between the channel region and the source electrode is identical to or different from a level of the schottky barrier between the channel region and the drain electrode.

Abstract translation: 提供一种半导体存储器件及其驱动方法，通过使用在沟道区域和源极/漏极之间的界面处形成的肖特基势垒来在沟道区域中存储电荷。 在硅衬底（100）的沟道区（130）上形成栅极（160）。 在硅衬底上形成源电极（110）和漏电极（120），以形成与沟道区域的肖特基结。 在源电极和漏电极之间形成的肖特基势垒中存储电荷。 源电极和漏电极由相同或不同的金属硅化物制成。 沟道区和源电极之间的肖特基结的电平与沟道区和漏电极之间的肖特基势垒的电平相同或不同。

公开(公告)号：KR100777101B1

公开(公告)日：2007-11-19

申请号：KR1020060074492

申请日：2006-08-08

Applicant: 한국전자통신연구원

Inventor： 전명심 ,  장문규 ,  김약연 ,  최철종 ,  박병철 ,  이성재

IPC: H01L21/335 ,  H01L29/872

Abstract: 본 발명은 비등방 에칭을 통해 생성되는 실리콘 (111)면(결정구조를 갖는 반도체에서 그 결정방향을 나타내는 밀러 지수)에 쇼트키 접합을 형성시켜 안정적이고, 전자에 대해 낮은 쇼트키 장벽을 갖는 고성능의 N-형 쇼트키 장벽 관통 트랜지스터를 제작하기 위한 것이다. 이를 위하여, 본 발명의 일실시 예에 따른 쇼트키 장벽 관통 트랜지스터는, 기판; 상기 기판 상에 형성된 소오스 및 드레인; 상기 소오스와 드레인 사이에 형성된 채널; 상기 채널 상에 순차적으로 형성된 게이트 절연막 및 게이트 전극;상기 게이트 절연막 및 게이트 전극의 양측 벽에 형성된 측벽 절연막을 포함하되, 상기 소오스 및 드레인과 상기 채널의 경계면은 실리콘 (111)면을 가지며, 상기 실리콘 (111)면, 소오스 및 드레인이 금속 물질로 실리사이드화되어 쇼트키 접합된다.
쇼트키 장벽 관통, 비등방 식각

公开(公告)号：KR100776648B1

公开(公告)日：2007-11-19

申请号：KR1020060123236

申请日：2006-12-06

Applicant: 한국전자통신연구원

Inventor： 장문규 ,  이성재 ,  최철종 ,  전명심 ,  김태엽 ,  김약연

IPC: H01L29/775

CPC classification number: H01L33/0004 ,  H01L27/15 ,  H01L33/06 ,  H01L33/16 ,  H01L33/34

Abstract: A silicon-based optical device and a method for manufacturing the same are provided to simplify a manufacturing process by using a general CMOS(Complementary Metal-Oxide Semiconductor) manufacturing method. A first and second transistors(100,101) are formed by using different conductive materials based on a silicon substrate(110), respectively. An active layer(119) is formed within the substrate between the first and second transistors. The active layer is formed with one quantum dot which is selected from a group including a silicon quantum dot formed within a silicon nitride layer, a silicon quantum dot formed within a silicon oxide layer, and a compound quantum dot. The compound quantum dot is selected from a group including GaAs, InAs, InGaAs, InAlAs, and InP. Each of the first and second transistors includes a gate insulating layer(113) formed on the substrate, gate electrodes(114A,114B) formed on the gate insulating layer, and a junction area(116) formed within the substrate exposed toward one side of the gate electrode.

Abstract translation: 提供硅基光学器件及其制造方法，以通过使用通用CMOS（互补金属氧化物半导体）制造方法来简化制造工艺。 第一和第二晶体管（100,101）分别通过使用基于硅衬底（110）的不同导电材料形成。 在第一和第二晶体管之间的衬底内形成有源层（119）。 有源层形成有一个量子点，其从包括在氮化硅层内形成的硅量子点的点，在氧化硅层内形成的硅量子点和化合物量子点组成。 化合物量子点选自包括GaAs，InAs，InGaAs，InAlAs和InP的组。 第一晶体管和第二晶体管中的每一个包括形成在基板上的栅极绝缘层（113），形成在栅极绝缘层上的栅电极（114A，114B）和形成在基板内的接合区域（116） 栅电极。

公开(公告)号：KR100698013B1

公开(公告)日：2007-03-23

申请号：KR1020050119409

申请日：2005-12-08

Applicant: 한국전자통신연구원

Inventor： 김약연 ,  이성재 ,  장문규 ,  최철종 ,  전명심 ,  박병철

IPC: H01L29/812

CPC classification number: H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

Abstract: A schottky barrier tunneling transistor and a method for manufacturing the same are provided to minimize leakage current of a gate by recovering damage of an insulating layer of a gate sidewall of the same according to a silicide process. A channel layer is formed on an upper surface of an SOI substrate(6). A source and drain(9) is formed at both ends of the channel layer on the SOI substrate. A gate(12) is formed on the channel layer. A first gate insulating layer is formed to shield the gate from the source and drain and the channel layer. A second gate insulating layer is formed between the first gate insulating layer and the gate.

Abstract translation: 提供肖特基势垒隧道晶体管及其制造方法，以通过根据硅化物处理来恢复其栅极侧壁的绝缘层的损坏来最小化栅极的漏电流。 沟道层形成在SOI衬底（6）的上表面上。 源极和漏极（9）形成在SOI衬底上的沟道层的两端。 在沟道层上形成栅极（12）。 形成第一栅极绝缘层以屏蔽栅极与源极和漏极以及沟道层。 在第一栅极绝缘层和栅极之间形成第二栅极绝缘层。