公开(公告)号：WO1998014023A1

公开(公告)日：1998-04-02

申请号：PCT/US1997017150

申请日：1997-09-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf, M. ,  SPAK, Michael, E.

IPC: H04Q07/32

CPC classification number: H04W88/02 ,  H04B1/0003 ,  H04B1/16 ,  H04B1/30 ,  H04B1/406 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/142 ,  Y02D70/40

Abstract: A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores (212), a microcontroller or microscheduler (222), a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU) (250). Each of the above devices are coupled to a system memory (202). The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory (262) and various peripheral devices (264) are coupled through a CPU local bus (260) to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter (252) is preferably coupled between the CPU and the system bus (214) and controls access to the system bus and the CPU local bus. The microscheduler operates to schedule operations and/or functions, as well as dynamically control the clock rates, of each of the DSPs and the hardware acceleration logic (240) to achieve the desired throughput while minimizing power consumption. The present invention thus provides a single architecture which has simplified configurability for different digital standards. The configurable digital communications architecture simplifies design and manufacturing costs and provides improved performance over prior designs.

Abstract translation: 一种可配置的多处理器通信架构，其执行数字通信功能并且可配置用于不同数字通信标准，例如各种数字蜂窝标准。 在优选实施例中，多处理器架构包括两个或多个数字信号处理核心（212），微控制器或微处理器（222），语音编码器/解码器（编解码器）和相对低性能的中央处理器（CPU）（250） ）。 上述每个设备耦合到系统存储器（202）。 通用CPU优选地执行用户界面功能和整体通信管理功能。 CPU本地存储器（262）和各种外围设备（264）通过CPU本地总线（260）耦合到CPU，并且CPU可访问这些设备，而CPU不必访问主系统总线。 双端口总线仲裁器（252）优选地耦合在CPU和系统总线（214）之间，并控制对系统总线和CPU本地总线的访问。 微调计器操作以调度操作和/或功能，以及动态地控制每个DSP和硬件加速逻辑（240）的时钟速率，以实现期望的吞吐量同时最小化功耗。 因此，本发明提供了一种具有简化的用于不同数字标准的可配置性的单一架构。 可配置的数字通信架构简化了设计和制造成本，并提供了比以前的设计更好的性能。

公开(公告)号：WO1998012631A1

公开(公告)日：1998-03-26

申请号：PCT/US1997016797

申请日：1997-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHUNG, Shine

IPC: G06F09/38

CPC classification number: G06F9/3806

Abstract: A microprocessor includes an instruction cache and a branch target buffer to implement a branch prediction scheme. The instruction cache, which stores branch instructions, is organized into cache lines and sets to implement set associative caching with memory that stores instructions. The branch target buffer includes storage locations organized into lines such that instructions stored in a cache line of the instruction cache correspond to a line in the branch target buffer. The storage locations permit storage of a branch target address that corresponds to any one of the sets in the cache line of the instruction cache to permit storage of branch information for multiple branch instructions when a cache line of a set stores more than one branch instruction. Thus, the resources of the branch target buffer are shared among the sets of the instruction cache.

Abstract translation: 微处理器包括指令高速缓存和分支目标缓冲器以实现分支预测方案。 存储分支指令的指令高速缓存组织成高速缓存行和集合，以与存储指令的存储器一起实现集合关联缓存。 分支目标缓冲器包括组织成行的存储位置，使得存储在指令高速缓存行中的指令对应于分支目标缓冲器中的一行。 当集合的高速缓存行存储多于一个分支指令时，存储位置允许存储对应于指令高速缓存的高速缓存行中的任何一个集合的分支目标地址以允许多个分支指令的分支信息的存储。 因此，分支目标缓冲器的资源在指令高速缓存的组之间被共享。

公开(公告)号：WO1998011610A1

公开(公告)日：1998-03-19

申请号：PCT/US1997016260

申请日：1997-09-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N.

IPC: H01L29/78

CPC classification number: H01L29/66621 ,  H01L29/7834 ,  Y10S257/90

Abstract: A field effect transistor comprising a semiconductor substrate (100) having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on floor of the transistor trench over a channel region (108) of the semiconductor substrate. A conductive gate structure (132) is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region (140a, 140b) of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 100-500 nm (1000-5000 angstroms) and a thickness of the conductive gate structure is less than 500 nm (5000 angstroms) such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate. The gate dielectric layer suitably comprises a thermal oxide having a thickness of approximately 2-20 nm (20-200 angstroms). In a lightly doped drain (LDD) embodiment, the source/drain impurity distribution includes a lightly doped region (146a, 146b) and a heavily doped region (138a, 138b). The lightly doped region extends laterally from the channel region of the transistor to the heavily doped region. In the preferred embodiment, a lateral dimension of the channel region of the transistor is approximately 100-300 nm.

Abstract translation: 一种场效应晶体管，包括具有从半导体衬底的上表面向下延伸的晶体管沟槽的半导体衬底（100）。 沟槽延伸到半导体衬底的上表面下方的沟槽深度。 晶体管还包括在半导体衬底的沟道区域（108）上形成在晶体管沟槽的底层上的栅极电介质层。 导电栅极结构（132）形成在栅极介电层的上方并与栅极电介质层接触。 在半导体衬底的源/漏区（140a，140b）内形成源/漏杂质分布。 源极/漏极区域横向地设置在半导体衬底的沟道区域的任一侧上。 在优选实施例中，沟槽深度在100-500nm（1000-5000埃）之间，并且导电栅极结构的厚度小于500nm（5000埃），使得导电栅极结构的上表面与 或者在半导体衬底的上表面之下。 栅介质层适当地包括厚度约为2-20nm（20-200埃）的热氧化物。 在轻掺杂漏极（LDD）实施例中，源极/漏极杂质分布包括轻掺杂区域（146a，146b）和重掺杂区域（138a，138b）。 轻掺杂区域从晶体管的沟道区域横向延伸到重掺杂区域。 在优选实施例中，晶体管的沟道区的横向尺寸约为100-300nm。

公开(公告)号：WO1998010470A1

公开(公告)日：1998-03-12

申请号：PCT/US1997015505

申请日：1997-09-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KADOSH, Daniel ,  GARDNER, Mark, I. ,  DAWSON, Robert

IPC: H01L29/78

CPC classification number: H01L29/66659 ,  H01L29/665 ,  H01L29/7835

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.

Abstract translation: 公开了一种包括轻掺杂和重掺杂漏极区域和超重掺杂源极区域的非对称IGFET。 优选地，轻掺杂漏极区域和超重掺杂源极区域提供通道结。 制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以基本上转换 将所有轻掺杂源区域全部掺入重掺杂源区，而不掺杂轻掺杂漏极区，形成与第二侧壁相邻的漏极侧隔离层，以及施加第三离子注入以将重掺杂源区转换成超掺杂源区， 并且将漏极侧间隔物外部的轻掺杂漏极区域的一部分转换为重掺杂漏极区域，而不将漏极侧间隔物下方的轻掺杂漏极区域的一部分掺杂。 有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

公开(公告)号：WO1998009408A1

公开(公告)日：1998-03-05

申请号：PCT/US1997006868

申请日：1997-04-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MANGIN, James, Lawrence ,  KADAMBI, Jayant ,  KALKUNTE, Mohan

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L47/13 ,  H04L47/263 ,  H04L47/283 ,  H04L49/351

Abstract: Delay times are modified in full-duplex Ethernet network devices by calculating in each network station a delay interval based on a size of a transmitted data packet and a desired transmission rate. The network station waits the calculated delay time before transmitting another data packet, ensuring that the overall output transmission rate of the network station corresponds to the assigned desired transmission rate. The desired transmission rate is received as a media access control (MAC) control frame from a network management entity, such as a switched hub. Hence, each station operates at the desired transmission rate, minimizing the occurrence of congestion and eliminating the necessity of PAUSE frames.

Abstract translation: 在全双工以太网网络设备中通过在每个网络站中计算基于所发送的数据分组的大小和期望的传输速率的延迟间隔来修改延迟时间。 在发送另一个数据包之前，网络站等待所计算的延迟时间，确保网络站的总输出传输速率对应于所分配的所需传输速率。 从诸如交换式集线器的网络管理实体接收期望的传输速率作为媒体访问控制（MAC）控制帧。 因此，每个站以期望的传输速率操作，使拥塞的发生最小化并且消除了暂停帧的必要性。

公开(公告)号：WO1998009325A1

公开(公告)日：1998-03-05

申请号：PCT/US1997009544

申请日：1997-06-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  KADOSH, Daniel

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: A semiconductor process in which spacer structures are used to reduce the minimum dimension of a shallow trench isolation structure. First and second spacer support structures are formed over first and second active regions within the semiconductor substrate, respectively. Thereafter, spacer structures are formed on side walls of the spacer support structures such that a trench region of the semiconductor substrate remains exposed. If the spacer support structures are formed a lateral distance from each other approximately equal to a minimum dimension of the photolithography apparatus, then the lateral dimension of the exposed region between the spacer structures is less than the minimum resolvable feature size of the photolithography apparatus. The isolation trench can then be etched into a trench region of the semiconductor substrate between the spacer structures. Thereafter, the trench is filled with an isolation dielectric and first and second transistors are formed within the first and second active regions respectively of the semiconductor substrate.

Abstract translation: 使用间隔结构来减小浅沟槽隔离结构的最小尺寸的半导体工艺。 分别在半导体衬底内的第一和第二有源区上形成第一和第二间隔物支撑结构。 此后，在间隔件支撑结构的侧壁上形成间隔结构，使得半导体衬底的沟槽区域保持暴露。 如果间隔件支撑结构形成彼此的横向距离，近似等于光刻设备的最小尺寸，则间隔结构之间的暴露区域的横向尺寸小于光刻设备的最小可分辨特征尺寸。 然后可以将隔离沟槽蚀刻到间隔物结构之间的半导体衬底的沟槽区域中。 此后，沟槽填充有隔离电介质，并且第一和第二晶体管分别形成在半导体衬底的第一和第二有源区域内。

公开(公告)号：WO1998008252A1

公开(公告)日：1998-02-26

申请号：PCT/US1997014881

申请日：1997-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LUNING, Scott ,  KUAN-YU LIU, David

IPC: H01L21/762

CPC classification number: H01L21/76221 ,  H01L21/32

Abstract: A local oxidation of silicon (LOCOS) process directed to forming differential field oxide thickness on a single wafer in one patterning step and one growth step. When patterning the masking layer, at least two window widths are formed in the masking layer, exposing the underlying substrate and pad oxide. When one of the window widths is sufficiently small, oxidation of the substrate will be inhibited causing reduced growth and thus a reduced field oxide thickness in that window as compared to other larger windows formed in the same masking layer, creating differential field oxide thicknesses in one growth step.

Abstract translation: 在一个图案化步骤和一个生长步骤中，局部氧化硅（LOCOS）工艺旨在在单个晶片上形成差分场氧化物厚度。 当图案化掩模层时，在掩模层中形成至少两个窗口宽度，暴露下面的衬底和衬垫氧化物。 当窗口宽度之一足够小时，与在相同掩模层中形成的其它较大的窗口相比，衬底的氧化将被抑制，导致生长减小并且因此减小了该窗口中的场氧化物厚度，从而在一个窗口中产生差异的场氧化物厚度 成长步骤

公开(公告)号：WO1998007163A1

公开(公告)日：1998-02-19

申请号：PCT/US1997009425

申请日：1997-05-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GITTINGER, Robert, Paul ,  SPILO, David, Allen

IPC: G11C29/00

CPC classification number: G11C29/36 ,  G11C29/48

Abstract: A microcontroller (10) includes an integrated memory (30) and an integrated DMA controller (20). During testing, the DMA controller (20) is used to perform read/write tests of background patterns and complements thereof to the integrated memory (30). The integrated memory (30) need not contain the BIST logic typically required of integrated memories. By using the DMA controller (20) to perform BIST-type testing, the tests are not hardware-bound. Typically, the BIST logic included in integrated memories is designed and tested during the design of the microcontroller. This design and test time is replaced by a (possibly shorter) task of generating test vectors for the requisite DMA transfers. The risk of having an error in the BIST test is reduced using the present testing method. Formerly, if BIST logic was found to be in error, new manufacturing masks for the microcontroller were required to repair the problem. A large time and monetary investment was required. The present method allows for correction and variation in the testing by resimulating the tests and creating new test vectors. The new test vectors may then be applied to previously manufactured microcontrollers.

Abstract translation: 微控制器（10）包括集成存储器（30）和集成DMA控制器（20）。 在测试期间，DMA控制器（20）用于对集成存储器（30）执行背景图案的读/写测试及其补充。 集成存储器（30）不需要包含通常需要的集成存储器的BIST逻辑。 通过使用DMA控制器（20）执行BIST类型测试，测试不受硬件限制。 通常，集成存储器中包含的BIST逻辑在微控制器的设计期间被设计和测试。 此设计和测试时间由为必要的DMA传输生成测试向量的（可能较短的）任务代替。 使用本测试方法可减少BIST测试中发生错误的风险。 以前，如果发现BIST逻辑错误，则需要新的微控制器制造掩模来修复问题。 需要大量的时间和货币投资。 本方法允许通过重新测试和创建新的测试向量来校正和变化测试。 然后可以将新的测试向量应用于先前制造的微控制器。

公开(公告)号：WO1998007090A1

公开(公告)日：1998-02-19

申请号：PCT/US1997009541

申请日：1997-06-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HANSEN, John, P.

IPC: G06F11/00

CPC classification number: G06F11/364

Abstract: A microcontroller integrates a memory accessible by the cores included thereon. Additionally the microcontroller provides an indication upon an external bus that accesses to the integrated memory are occurring. The indication provides a ready identification of internal access cycles. In one embodiment, the indication is multiplexed with a control signal upon the external bus. The microcontroller further employs a show read bus transfer, which may be optionally enabled by the user. The show read bus transfer transmits upon the external bus the read data being provided from the internal memory to a core. The cycle is presented with identical functional timing to normal read cycles. Additionally, the A/C timings of the show read bus transfer are consistent with external read transfers. Therefore, external circuitry (such as an in-circuit emulator) may capture the data from the show read bus transfer using the same circuitry used to capture external read data. The show read bus transfer may be enabled by setting a configuration register bit within the microcontroller, or by asserting a signal upon a predefined pin at the conclusion of reset of the microcontroller. By providing the predefined pin for activating the show read mode of the microcontroller, the microcontroller may be placed into show read mode for debug purposes without changing the instruction code being executed thereon.

Abstract translation: 微控制器集成了由其上包括的核可访问的存储器。 此外，微控制器在外部总线上提供对集成存储器进行访问的指示。 该指示提供了内部访问周期的准备状态。 在一个实施例中，该指示与外部总线上的控制信号多路复用。 微控制器还采用显示读总线传输，其可由用户可选地启用。 显示读取总线传输在外部总线上传送从内部存储器提供的读取数据到核心。 该周期具有与正常读取周期相同的功能定时。 此外，显示读取总线传输的A / C时序与外部读取传输一致。 因此，外部电路（如在线仿真器）可以使用与捕获外部读取数据相同的电路从显示读取总线传输中捕获数据。 可以通过在微控制器内设置配置寄存器位或者在微控制器复位结束时通过在预定义的引脚上断言信号来启用显示读总线传输。 通过提供用于激活微控制器的显示读取模式的预定义引脚，可以将微控制器置于显示读取模式以进行调试，而不改变在其上执行的指令代码。

公开(公告)号：WO1998006202A1

公开(公告)日：1998-02-12

申请号：PCT/US1997003417

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Lawrence ,  MERCHANT, Shashank, Chandravadan

IPC: H04L12/413

CPC classification number: H04L12/40156 ,  H04L12/413 ,  H04L12/6418 ,  H04L2012/6435 ,  H04L2012/6448 ,  H04L2012/6454 ,  H04L2012/6464

Abstract: Collision delay intervals are modified in Ethernet network devices transmitting priority data requiring a guaranteed latency by multiplying an integer multiple number of slot times with a fractional coefficient (92). A network device having priority data for transmission uses the conventional Truncated Binary Exponential Backoff (TREB) algorithm during the first access attempt to calculate a collision delay interval from a randomly selected integer multiple of slot times (88). If the network device encounters another collision (102), the next randomly selected integer multiple of slot times is multiplied by the fractional coefficient (92). Use of the fractional coefficient during collision mediation on a half-duplex Ethernet provides a bounded access latency for real-time and multimedia applications by granting the network device a higher probability of successfully accessing the network media.

Abstract translation: 在以太网网络设备中，通过将整数倍数的时隙乘以分数系数（92）来传送需要保证等待时间的优先级数据，在以太网网络设备中修改冲突延迟时间间隔。 具有传输优先权数据的网络设备在第一次接入尝试期间使用传统的截断二进制指数退避（TREB）算法来计算随机选择的时隙倍数（88）的冲突延迟间隔。 如果网络设备遇到另一个冲突（102），则将时隙时间的下一个随机选择的整数倍乘以分数系数（92）。 在半双工以太网以太网以太网交换机之间的冲突中介中使用分数系数通过授予网络设备成功访问网络媒体的可能性更高，为实时和多媒体应用提供有限的访问延迟。