公开(公告)号：EP1356505A1

公开(公告)日：2003-10-29

申请号：EP01957475.5

申请日：2001-08-06

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  HE, Yue-Song ,  THURGATE, Timothy ,  CHANG, Chi ,  WONG, Ngaching

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/66833

Abstract: One aspect of the present invention relates to a method of making a flash memory cell (32), involving providing a substrate (30) having a flash memory cell (32) thereon; forming a self-aligned source mask (48) over the substrate, the self aligned source mask (48) having openings (50) corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings (50) in the self-aligned source mask (48) corresponding to source lines (52); removing the self-aligned source mask (48) from the substrate (30); forming a MDD mask (54) over the substrate (30), the MDD mask (54) covering the source lines (52) and having openings (56) corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region (58) in the substrate (30) adjacent the flash memory cell (32).

公开(公告)号：EP1142014A1

公开(公告)日：2001-10-10

申请号：EP99972785.2

申请日：1999-10-27

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FLIESLER, Michael, David ,  RANDOLPH, Mark, W.

IPC: H01L21/8239 ,  H01L27/02

CPC classification number: H01L27/11526 ,  H01L27/0266 ,  H01L27/11534

Abstract: In a non-volatile memory comprising a region (2) for core memory cells and a peripheral region (4a) on a substrate (6), a method for improving the electrostatic discharge (ESD) robustness of the non-volatile memory comprises the steps of lightly doping the source region (18) and the drain region (20) of a peripheral transistor (12) in the peripheral region (4a) with a first n-type dopant, providing a double diffusion implant mask (10) having an opening over the region (2) for the core memory cells and also an opening (8) over the peripheral region (4a), and performing a double diffusion implantation through the opening (8) over the peripheral region (4a). In an embodiment, the step of performing the double-diffusion implantation comprises the steps of implanting a second n-type dopant comprising phosphorus into the source and drain regions (18) and (20), and implanting a third n-type dopant comprising arsenic into the source and drain regions (18) and (20) subsequent to the step of implanting the second n-type dopant.

公开(公告)号：EP1709682A1

公开(公告)日：2006-10-11

申请号：EP04814984.3

申请日：2004-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

IPC: H01L21/8246 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/792 ,  H01L29/10

CPC classification number: H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

公开(公告)号：EP1568085A1

公开(公告)日：2005-08-31

申请号：EP03812414.5

申请日：2003-07-10

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： RANDOLPH, Mark, W. ,  CHANG, Chi ,  HE, Yi ,  ZHENG, Wei ,  RUNNION, Edward, F.

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  G11C16/0475 ,  G11C16/14 ,  H01L29/7923

Abstract: The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well (510) is formed in a semiconductor substrate (529). A plurality of N-type impurity concentrations (550, 555) are formed in the isolated P-well (510) and a nitride memory cell (560) is fabricated between two of the N-type impurity concentrations (550, 555). Finally, an electrical contact (590) is coupled to the isolated P-well (510).

公开(公告)号：EP1568037A1

公开(公告)日：2005-08-31

申请号：EP03748970.5

申请日：2003-07-24

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HE, Yi ,  LIU, Zhizheng ,  RANDOLPH, Mark, W. ,  RUNNION, Edward, F. ,  HAMILTON, Darlene ,  CHEN, Patu-Ling ,  LE, Binh, Q.

IPC: G11C7/12 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C7/12 ,  G11C16/0475 ,  G11C16/24

Abstract: A method of detecting a charge stored on a charge storage region (62) of a first dual bit dielectric memory cell (49) within an array (40) of dual bit dielectric memory cells (48) comprises coupling a first bit line (201) that forms a source junction with a channel region (50) of the first memory cell (49) to ground (68). A high voltage is applied to a gate (60) of the first memory cell (49) and to a second bit line (202) that is the next bit line to the right of the first bit line (201) and separated from the first bit line (201) only by the channel region (50). A third bit line (203), that is the next bit line to the right of the second bit line (202), is isolated such that its potential is effected only by its junctions with the a second channel region (50) and a third channel region (50) on opposing sides of the third bit line (203). A high voltage is applied to a pre-charge bit line that is to the right of the third bit line (203) and current flow is detected at the second bit line (202) to determine the programmed status of a source bit (62) of the first memory cell (49).

公开(公告)号：EP1568043A1

公开(公告)日：2005-08-31

申请号：EP03755728.7

申请日：2003-07-24

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HE, Yi ,  LIU, Zhizheng ,  RANDOLPH, Mark, W. ,  HADDAD, Sameer, S.

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0475 ,  G11C16/0491

Abstract: An array (40) of dual bit dielectric memory cells (48) comprises a plurality of bit lines. A first bit line (201) forms a source region for each of a plurality of memory cells (38) within a column of memory cells within the array (40). A second bit line (202) forms a drain region for each of the plurality of memory cells (38) within the column. A channel region (50) of the opposite conductivity is positioned between the first bit line (201) and the second bit line (202) and forms a junction with each. A selected word line (211) is positioned over the channel region (50) and forms a gate (60) over each for a plurality of memory cells (48) within a same row. A plurality of non-selected word lines (210, 212), are each parallel to the selected word line (211) and each form a gate (60) over one of the plurality of memory cells (48) within the column other than the selected one of the plurality of memory cells (49). A word line control circuit (46) applies a positive programming voltage (220) to the selected word line (211) while a bit line control circuit (44) simultaneously applies a positive drain voltage to the drain bit line (202) and a positive source voltage to the source bit line (201), the positive source voltage being less than the positive drain voltage.

公开(公告)号：EP1282915A2

公开(公告)日：2003-02-12

申请号：EP01931005.1

申请日：2001-05-01

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： RANDOLPH, Mark, W. ,  HOLLMER, Shane, Charles ,  CHEN, Pau-Ling ,  FASTOW, Richard, M.

IPC: H01L21/8246

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: An array of memory cells that includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines (224), wherein M = 2, 3, 4, 5,... and each of the M bitlines (224) is buried. The array further includes a plurality of contacts (228), wherein each of the plurality of contacts (228) is formed every N wordlines, N = 1, 2, 3,..., wherein each of the plurality of contacts (228) overlies a gate (229) of a different one of the plurality of memory cells. A strap (231) connects one of the buried bitlines (224) to a gate (229) that underlies one of the plurality of contacts (228) and a select transistor (232) is formed every P wordlines, wherein P is greater than N.