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    11.
    发明专利
    未知

    公开(公告)号：AT493793T

    公开(公告)日：2011-01-15

    申请号：AT06017779

    申请日：2006-08-25

    Applicant: ALTERA CORP

    Inventor： LAI TIN ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  WONG WILSON

    IPC: H03G3/20 ,  H04L25/03

    Abstract: Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.

    High-speed serial data signal transmitter driver circuitry
    18.
    发明专利
    High-speed serial data signal transmitter driver circuitry 审中-公开
    高速串行数据信号发射机驱动电路

    公开(公告)号：JP2009147948A

    公开(公告)日：2009-07-02

    申请号：JP2008320310

    申请日：2008-12-16

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： WONG WILSON ,  CHAN ALLEN ,  SHUMARAYEV SERGEY ,  DING WEIQI

    IPC: H03K19/0175 ,  H04L25/02

    CPC classification number: H04L25/028

    Abstract: PROBLEM TO BE SOLVED: To provide high-speed serial digital data signal transmitter driver circuitry.
    SOLUTION: The present invention relates to transmitter driver circuitry for outputting a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps, including H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor forming a portion of the H-tree driver circuitry further provides electrostatic discharge protection for the circuitry.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供高速串行数字数据信号发射器驱动电路。 解决方案：本发明涉及用于输出具有约10Gbps范围内的串行比特率的高速串行数据信号的发射机驱动器电路，包括仅具有主驱动级和后级的H树驱动器电路 tap驱动阶段。 形成H树驱动器电路的一部分的至少一个晶体管进一步为电路提供静电放电保护。 版权所有（C）2009，JPO＆INPIT

    Digital adaptation circuitry and method for programmable logic devices
    19.
    发明专利
    Digital adaptation circuitry and method for programmable logic devices 审中-公开
    数字适应电路和可编程逻辑器件的方法

    公开(公告)号：JP2008072716A

    公开(公告)日：2008-03-27

    申请号：JP2007237202

    申请日：2007-09-12

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

    IPC: H04B3/14 ,  H04B3/06 ,  H04L25/03

    CPC classification number: H04L25/03885

    Abstract: PROBLEM TO BE SOLVED: To provide digital adaptation circuitry and method for programmable logic devices.
    SOLUTION: This method provides for controlling equalization of an incoming data signal. The method includes detecting two successive differently valued bits in the data signal, determining whether transition in the incoming data signal between those bits occurs relatively late or relatively early, and increasing the equalization of the incoming data signal if it is relatively late.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：为可编程逻辑器件提供数字适配电路和方法。 解决方案：该方法用于控制输入数据信号的均衡。 该方法包括检测数据信号中的两个连续的不同值的位，确定这些位之间的输入数据信号中的转换是否相对较晚或相对较早地发生，如果相对较晚，则增加输入数据信号的均衡。 版权所有（C）2008，JPO＆INPIT

    High-speed data receiving circuit network and method
    20.
    发明专利
    High-speed data receiving circuit network and method 有权
    高速数据接收电路和方法

    公开(公告)号：JP2007037114A

    公开(公告)日：2007-02-08

    申请号：JP2006187052

    申请日：2006-07-06

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SHUMARAYEV SERGEY Y ,  WONG WILSON ,  PATEL RAKESH

    IPC: H04L25/03 ,  H04B3/06

    CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit network which compensates losses, such as decrease in signal amplitude and abrupt changes, in order to maintain accurate and high-speed data transmission.
    SOLUTION: An equalizing circuit network (10), receiving a digital data signal, includes both a feedforward equalizer (FFE)(30) and a determination feedback equalizer (DFE)(90). The FFE circuit network (30) is used for providing at least sufficient minimum signal to the DFE circuit network (90) and an adequate startup of the DFE circuit network (90). Accordingly, the heavier the load of an equalizing task is, the more the task can be shifted, from the FFE circuit network (30) to the DFE circuit network (90).
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供补偿诸如信号幅度和突然变化的损失的电路网络，以便保持精确和高速的数据传输。 解决方案：接收数字数据信号的均衡电路网络（10）包括前馈均衡器（FFE）（30）和确定反馈均衡器（DFE）（90）。 FFE电路网络（30）用于向DFE电路网络（90）提供至少足够的最小信号和DFE电路网络（90）的适当启动。 因此，平衡任务的负担越重，任务可以从FFE电路网络（30）到DFE电路网络（90）的移动越多。 版权所有（C）2007，JPO＆INPIT

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