公开(公告)号：JPH09129722A

公开(公告)日：1997-05-16

申请号：JP26699796

申请日：1996-10-08

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRANCO GIOVANNI ,  CAMALLERI CATENO MARCO ,  FRISINA FERRUCCIO

IPC: H01L21/761 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

Abstract: PROBLEM TO BE SOLVED: To provide an electric power device wherein high yield efficiency is obtained with low ion implantation energy and provided with a deep edge ring by, with the use of a boron and Al as a dopant, forming a deep ring at the same time for the main body of a device in a single thermal process, and further, an oxide layer used during Al ion implantation. SOLUTION: On a heavily doped N type substrate 10, a slightly doped N type epitaxial layer 20 is grown, further, over the upper part of the epitaxial layer 20, an oxide 30 is grown. By photo-etching, an main body is exposed itself in an area 30, and boron 40 is implanted for a p are 42 to be generated. Then, oxide etching is performed, the area for Al ion implantation is made exposed, thus an Al ring is configured. By masking the main body area with a photosensitive material layer, an Al ion 60 is implanted. Then, through a single thermal diffusion process, P /N joint 80 formed through formation of a thermal oxide layer 70 and boron, and one or more P /N joints 90 formed by Al are formed at the same time.

公开(公告)号：JPH0817849A

公开(公告)日：1996-01-19

申请号：JP15598395

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: PURPOSE: To reduce the manufacturing process of the channel region of a basic function unit and to reduce the ON resistance of a power device by forming the deep body part and the channel part of a body region only by ion implantation without performing any thermal diffusion treatment. CONSTITUTION: After a first dopant is selectively ion-implanted into a heavily doped part 5 in a direction that orthogonally crosses a semiconductor surface with a proper amount of dosage and an energy of ion implantation with an insulation gate layer 8 as a mask, a second dopant is selectively ion-implanted into a region 6 along a direction that is inclined at a prescribed angle in an orthogonally crossed direction, thus forming a body region 2. Then, a large dosage of third dopant is ion-implanted into the greatly doped part 5 to form a source region 7 that is nearly aligned to the edge part of the insulation gate layer 8, thus reducing the manufacturing process of the channel region of a basic function unit since no thermal diffusion treatment is made and reducing the on resistance of a power device.

公开(公告)号：DE69518653D1

公开(公告)日：2000-10-05

申请号：DE69518653

申请日：1995-12-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONINO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：DE69324003T2

公开(公告)日：1999-07-15

申请号：DE69324003

申请日：1993-06-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  COFFA SALVATORE

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/167 ,  H01L29/73 ,  H01L29/732

Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate (1) of the N type over which a lightly doped N type layer (2), constituting a collector region of the transistor, is superimposed; the transistor has a base region comprising a heavily doped P type diffusion (4) which extends into the lightly doped N type layer (2) from a top surface, and an emitter region constituted by a heavily doped N type diffusion (11) extending from said top surface within said heavily doped P type diffusion (4); the heavily doped P type diffusion (4) is obtained within a deep lightly doped P type diffusion (3), extending from said top surface into the lightly doped N type layer (2) and formed with acceptor impurities represented by atoms of aluminium.

公开(公告)号：DE69418037D1

公开(公告)日：1999-05-27

申请号：DE69418037

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L21/60 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L29/72

Abstract: In a MOS-technology power device chip and package assembly, the MOS-technology power device chip (1) comprises a semiconductor material layer (4,5) in which a plurality of elementary functional units (6) is integrated, each elementary functional unit (6) contributing for a respective fraction to an overall current and comprising a first doped region (7) of a first conductivity type formed in said semiconductor layer (4,5), and a second doped region (10) of a second conductivity type formed inside said first doped region (7); the package (2) comprises a plurality of pins (P1-P10) for the external electrical and mechanical connection; said plurality of elementary functional units (6) is composed of sub-pluralities of elementary functional units (6), the second doped regions (10) of all the elementary functional units (6) of each sub-plurality being contacted by a same respective metal plate (100) electrically insulated from the metal plates (100) contacting the second doped regions (10) of all the elementary functional units (6) of the other sub-pluralities; each of said metal plate (100) is connected, through a respective bonding wire (W1-W5), to a respective pin (P1-P5) of the package (2).

公开(公告)号：DE69321966D1

公开(公告)日：1998-12-10

申请号：DE69321966

申请日：1993-12-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MANGIAGLI MARCANTONIO

IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

Abstract: An integrated structure pad assembly for lead bonding to a power semiconductor device chip comprises a chip portion having a top surface covered by a metallization layer (10) and which comprises a first sub-portion (1) wherein functionally active elements of the power device are present; said chip portion comprises at least one second sub-portion (11) wherein no functionally active elements of the power device are present, and a top surface of the metallization layer (10) is elevated over said at least one second sub-portion (11) with respect to the first sub-portion (1) to form at least one protrusion which forms a support surface for a lead.

公开(公告)号：DE69117889T2

公开(公告)日：1996-09-05

申请号：DE69117889

申请日：1991-11-16

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  TAVOLO NELLA ,  RASPAGLIESI MARIO

IPC: H01L21/322 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/167

公开(公告)号：DE69434937D1

公开(公告)日：2007-04-19

申请号：DE69434937

申请日：1994-06-23

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: A zero thermal budget process for the manufacturing of a MOS-technology vertical power device (such as a MOSFET or a IGBT) comprises the steps of: forming a conductive Insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (3) of a first conductivity type; selectively removing the insulated gate layer (8) from selected portions of the semiconductor material layer (3) surface; selectively implanting a first dopant of a second conductivity type into said selected portions of the semiconductor material layer (3), the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, heavily doped regions (5) substantially aligned with the edges of the insulated gate layer (8); selectively implanting a second dopant of the second conductivity type along directions tilted of prescribed angles ( alpha 1, alpha 2) with respect to a direction orthogonal to the semiconductor material layer (3) surface, the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, lightly doped channel regions (6) extending under the insulated gate layer (8); selectively implanting a heavy dose of a third dopant of a first conductivity type into the heavily doped regions (5), to form source regions (7) substantially aligned with the edges of the insulated gate layer (8).

公开(公告)号：DE69429915D1

公开(公告)日：2002-03-28

申请号：DE69429915

申请日：1994-07-04

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

公开(公告)号：DE69324003D1

公开(公告)日：1999-04-22

申请号：DE69324003

申请日：1993-06-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  COFFA SALVATORE

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/167 ,  H01L29/73 ,  H01L29/732

Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate (1) of the N type over which a lightly doped N type layer (2), constituting a collector region of the transistor, is superimposed; the transistor has a base region comprising a heavily doped P type diffusion (4) which extends into the lightly doped N type layer (2) from a top surface, and an emitter region constituted by a heavily doped N type diffusion (11) extending from said top surface within said heavily doped P type diffusion (4); the heavily doped P type diffusion (4) is obtained within a deep lightly doped P type diffusion (3), extending from said top surface into the lightly doped N type layer (2) and formed with acceptor impurities represented by atoms of aluminium.